ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D)
ANALOG TO DIGITAL CONVERTER (Cont’d)
INTERRUPT CONTROL REGISTER (AD_ICR)
R254 - Read/Write
Register Page: 63
Bit 4 = AWDI: Analog Watchdog Interrupt Enable.
This bit masks or enables the Analog Watchdog
interrupt request.
Reset Value: 0000 1111 (0Fh)
0: Mask Analog Watchdog interrupts
1: Enable Analog Watchdog interrupts
7
0
ECV AWD ECI AWDI
X
PL2 PL1 PL0
Bit 3 = Reserved.
Bit 2:0 = PL[2:0]: A/D Interrupt Priority Level.
These three bits allow selection of the Interrupt pri-
ority level for the A/D.
Bit 7 = ECV: End of Conversion.
This bit is set by hardware after a group of conver-
sions is completed. It must be reset by the user,
before returning from the Interrupt Service Rou-
tine. Setting this bit by software will cause a soft-
ware interrupt request to be generated.
0: No End of Conversion event occurred
1: An End of Conversion event occurred
INTERRUPT VECTOR REGISTER (AD_IVR)
R255 - Read/Write
Register Page: 63
Reset Value: xxxx xx10 (x2h)
Bit 6 = AWD: Analog Watchdog.
7
0
0
This is automatically set by hardware whenever ei-
ther of the two monitored analog inputs goes out of
bounds. The threshold values are stored in regis-
ters F8h and FAh for channel 6, and in registers
F9h and FBh for channel 7 respectively. The Com-
pare Result Register (CRR) keeps track of the an-
alog inputs exceeding the thresholds.
V7
V6
V5
V4
V3
V2
W1
Bit 7:2 = V[7:2]: A/D Interrupt Vector.
This vector should be programmed by the User to
point to the first memory location in the Interrupt
Vector table containing the starting addresses of
the A/D interrupt service routines.
The AWD bit must be reset by the user, before re-
turning from the Interrupt Service Routine. Setting
this bit by software will cause a software interrupt
request to be generated.
0: No Analog Watchdog event occurred
1: An Analog Watchdog event occurred
Bit 1 = W1: Word Select.
This bit is set and cleared by hardware, according
to the A/D interrupt source.
0: Interrupt source is the Analog Watchdog, point-
ing to the lower word of the A/D interrupt service
block (defined by V[7:2]).
1:Interrupt source is the End of Conversion inter-
rupt, thus pointing to the upper word.
Bit 5 = ECI: End of Conversion Interrupt Enable.
This bit masks the End of Conversion interrupt re-
quest.
0: Mask End of Conversion interrupts
1: Enable End of Conversion interrupts
Note: When two requests occur simultaneously,
the Analog Watchdog Request has priority over
the End of Conversion request, which is held
pending.
Bit 0 = Reserved. Forced by hardware to 0.
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ETC [ ETC ]
