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ST72254G1B1 参数 Datasheet PDF下载

ST72254G1B1图片预览
型号: ST72254G1B1
PDF下载: 下载PDF文件 查看货源
内容描述: 与单电压闪存的8位MCU 。 ADC。 16位定时器。 SPI 。\n [8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY. ADC. 16-BIT TIMERS. SPI. ]
分类和应用: 闪存
文件页数/大小: 140 页 / 1350 K
品牌: ETC [ ETC ]
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ST72104G, ST72215G, ST72216G, ST72254G  
12.3 SERIAL PERIPHERAL INTERFACE (SPI)  
12.3.1 Introduction  
12.3.3 General description  
The Serial Peripheral Interface (SPI) allows full-  
duplex, synchronous, serial communication with  
external devices. An SPI system may consist of a  
master and one or more slaves or a system in  
which devices may be either masters or slaves.  
The SPI is connected to external devices through  
4 alternate pins:  
– MISO: Master In Slave Out pin  
– MOSI: Master Out Slave In pin  
– SCK: Serial Clock pin  
The SPI is normally used for communication be-  
tween the microcontroller and external peripherals  
or another microcontroller.  
– SS: Slave select pin  
Refer to the Pin Description chapter for the device-  
specific pin-out.  
A basic example of interconnections between a  
single master and a single slave is illustrated on  
Figure 37.  
12.3.2 Main Features  
The MOSI pins are connected together as are  
MISO pins. In this way data is transferred serially  
between master and slave (most significant bit  
first).  
Full duplex, three-wire synchronous transfers  
Master or slave operation  
Four master mode frequencies  
Maximum slave mode frequency = fCPU/2.  
Four programmable master bit rates  
Programmable clock polarity and phase  
End of transfer interrupt flag  
When the master device transmits data to a slave  
device via MOSI pin, the slave device responds by  
sending data to the master device via the MISO  
pin. This implies full duplex transmission with both  
data out and data in synchronized with the same  
clock signal (which is provided by the master de-  
vice via the SCK pin).  
Write collision flag protection  
Master mode fault protection capability.  
Thus, the byte transmitted is replaced by the byte  
received and eliminates the need for separate  
transmit-empty and receiver-full bits. A status flag  
is used to indicate that the I/O operation is com-  
plete.  
Four possible data/clock timing relationships may  
be chosen (see Figure 40) but master and slave  
must be programmed with the same timing mode.  
Figure 37. Serial Peripheral Interface Master/Slave  
MASTER  
SLAVE  
MSBit  
LSBit  
MSBit  
LSBit  
MISO  
MOSI  
MISO  
MOSI  
8-BIT SHIFT REGISTER  
8-BIT SHIFT REGISTER  
SPI  
CLOCK  
SCK  
SCK  
GENERATOR  
SS  
SS  
+5V  
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