ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
12.2.4 Low Power Modes
Mode
WAIT
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
HALT
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
12.2.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
12.2.6 Summary of Timer modes
AVAILABLE RESOURCES
MODES
Input Capture 1
Input Capture 2
Yes
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse mode
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
PWM Mode
No
No
1)
2)
3)
See note 4 in Section 12.2.3.5 "One Pulse Mode" on page 54
See note 5 in Section 12.2.3.5 "One Pulse Mode" on page 54
See note 4 in Section 12.2.3.6 "Pulse Width Modulation Mode" on page 56
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ETC [ ETC ]
