RTL8211C & RTL8211CL
Datasheet
6.2.2. RGMII (100Mbps) Mode
The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing
recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the RGMII
interface in 4-bit-wide nibbles at a clock speed of 25MHz.
6.2.3. RGMII (10Mbps) Mode
The received differential signal is converted into a Manchester-encoded stream first. Next, the stream is
processed with a Manchester decoder, and is de-serialized into 4-bit-wide nibbles. The 4-bit nibbles are
presented to the RGMII interface at a clock speed of 2.5MHz.
6.3. Hardware Configuration
The operation speed, interface mode, and PHY address can be set by the CONFIG pins. The respective
value mapping of CONFIG with the configurable vector is listed in Table 11. To set the CONFIG pins, an
external pull-high or pull-low via resister is required.
Table 11. CONFIG Pins vs. Configuration Register
RTL8211C Pin
LED Link 10
LED Link 1000
RXD2
RTL8211CL Pin
LED0
Pin Name
PHYAD[0]
PHYAD[1]
AN[0]
LED1
RXD2
RXD3
RXD3
AN[1]
Table 12. Configuration Register Definition
Configuration Description
PHYAD[1:0]
PHY Address.
PHYAD sets the PHY address for the device.
Note: PHYAD[:]=0 can support all PHYaddresses. It can automatically remember the first MAC address.
Auto-Negotiation (NWay) Configuration.
AN[1:0]
AN[1:0] controls the setting of Auto-Negotiation enable/disable, speed, and duplex setting.
00: 10Base-T Full Duplex
01: 100base-Tx Half Duplex
10: 100base-Tx Full Duplex
11: NWay. Advertise all capabilities
Integrated 10/100/1000 Gigabit Ethernet Transceiver
10
Track ID: JATR-1076-21 Rev. 1.3
ETC [ ETC ]
