RTL8211C & RTL8211CL
Datasheet
6.5. MAC/PHY Interface
The RTL8211C(L) supports industry standard and is suitable for most off-the-shelf MACs with a RGMII
interface.
6.5.1. RGMII
In 1000Base-T mode (RGMII interface is selected), TXC and RXC sources are 125MHz. TXC will always
be generated by the MAC and RXC will always be generated by the PHY. TXD[3:0] and RXD[3:0] signals
are used for date transitions on rising edge and on falling edge of clock.
6.5.2. Management Interface
The management interface provides access to the internal registers through the MDC and MDIO pins as
described in IEEE 802.3u section 22. The MDC signal, provided by the MAC, is the management data
clock reference to the MDIO signal. The MDIO is the management data input/output and is a bi-directional
signal that runs synchronously to MDC. The MDIO pin needs a 10k Ohm pull-up resistor to maintain the
MDIO high during idle and turnaround.
Preamble suppression is the default setting of the RTL8211C(L) after power-on. However, there still must
be at least one idle bit between operations.
Up to 32 RTL8211C(L)s can share the same MDIO line. In switch/router applications, each port should be
assigned a unique address during the hardware reset sequence, and it can only be addressed via that unique
PHY address. For detailed information on the RTL8211C(L) management registers, see section 7 Register
Descriptions, page 22.
Table 13. Typical MDIO Frame Format
<idle><start><op code><PHY addr.><reg. addr.><turnaround><data><idle>
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
Management Serial Protocol
Read
Write
MDC
z
z
MDIO(MAC)
z
MDIO(PHY)
z
z
z
1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
Read
(OP
Code)
Idle Start
PHY Address
0x01
Reg. Address
0x00 (BMCR)
Turn
Around
Reg. Data
0x1140
Idle
Figure 4. Typical MDC/MDIO Read Timing
Integrated 10/100/1000 Gigabit Ethernet Transceiver
12
Track ID: JATR-1076-21 Rev. 1.3
ETC [ ETC ]
