RDA Microelectronics, Inc.
RDA5807SP FM Tuner V1.0
3
Functional Description
Figure 3-1. RDA5807SP FM Tuner Block Diagram
The DSP core finishes the channel selection, FM
demodulation, stereo MPX decoder and output
audio signal. The MPX decoder can autonomous
switch from stereo to mono to limit the output
noise.
3.1
FM Receiver
The receiver uses a digital low-IF architecture that
avoids the difficulties associated with direct
conversion while delivering lower solution cost
and reduces complexity, and integrates a low
noise amplifier (LNA) supporting the FM
broadcast band (76 to 108MHz), a quadrature
image-reject mixer, a programmable gain control
The DACs convert digital audio signal to analog
and change the volume at same time. The DACs
has low-pass feature and -3dB frequency is about
30 KHz.
(PGA),
a
high resolution analog-to-digital
converters (ADCs), an audio DSP and a high-
fidelity digital-to-analog converters (DACs).
3.2
Synthesizer
The LNA has differential input ports (LNAP and
LNAN). The LNA default input resistance is 150
Ohm under single or dual input mode. It default
input common mode voltage is GND.
The frequency synthesizer generates the local
oscillator signal which divide to quadrature, then
be used to down convert the RF input to a
constant low intermediate frequency (IF). The
synthesizer reference clock is 32.768 KHz,12M,
24M, 13M, 26M, 19.2M, 38.4MHz. select by CLK MODE[2:0]
BIT.
The limiter prevents overloading and limits the
amount of intermodulation products created by
strong adjacent channels.
The quadrature mixer down converts the LNA
output differential RF signal to low-IF, it also has
image-reject function.
3.3
Power Supply
The RDA5807SP integrated one LDO which
supplies power to the chip. The external supply
voltage range is 2.7-5.5 V.
The PGA amplifies the mixer output IF signal and
then digitized with ADCs.
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part without prior written permission of RDA.
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