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PMD100 参数 Datasheet PDF下载

PMD100图片预览
型号: PMD100
PDF下载: 下载PDF文件 查看货源
内容描述: - 12号的铝制车身绘( RAL 7032 ) []
分类和应用:
文件页数/大小: 25 页 / 1324 K
品牌: ETC [ ETC ]
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®
PMD-100  
PMD-100 Process Decoder  
Pin Description (Stand-Alone Mode) -  
Pin 9 Low  
( I = Input, O = Output. All input levels TTL compatible  
except XTI which must be CMOS level. No inputs have  
pull-ups. All outputs are full CMOS levels. )  
1:  
2:  
3:  
DIN (I)  
BCKI (I)  
XTIM (I)  
Serial data input.  
Bit clock input.  
Select system clock frequency.  
Low = 256 Fs, High = 384 Fs.  
Dither select.  
4:  
DITH (I)  
Low = dither disabled,  
High = dither added.  
5:  
GAIN (O) Analog output stage gain.  
Use only if Pin 19 is High (see page  
14).  
Low = low gain,  
High = high gain (+6 dB).  
(See pin 19 description).  
System clock input.  
+5 volt power for filter.  
Ground  
Select Program mode.  
Low = Stand-Alone,  
High = Program.  
6:  
7:  
8:  
9:  
XTI (I)  
VDD1  
VSS1  
PROG(I)  
Low = off, High = on.  
17: HMUTE (I) Hard mute. Low = off, High = on.  
18: FSEL (I)  
De-emphasis filter Fs.  
Low = 44.1 kHz, High = 48 kHz.  
Gain scaling.  
Note: Pins 10 through 14 perform different functions  
depending on whether Stand-Alone or Program mode is  
selected.  
19: SCAL (I)  
Low = 6dB gain scaling is performed  
internally in the digital domain,  
High = analog output gain stage is set  
by pin 5 GAIN. (See page 14.)  
Stand-Alone Mode:  
10: OSIZ0 (I)  
20: DG (O) DAC sample and hold deglitch signal.  
11: OSIZ1 (I)  
21: VSS2  
22: VDD2  
Ground. (Common with VSS1)  
+5 volt power for output interface.  
These two pins determine the output word size, as well as  
the number of pulses on BCKO.  
23: DOR (O) Right channel serial data output.  
24: DOL (O) Left channel serial data output.  
25: WCKO(O) Word clock output.  
26: BCKO (O) Bit clock output.  
27: HDCD (O) HDCD encoding detect.  
Low = no encoding. High = HDCD  
12: COB (I)  
13: JUST (I)  
Output data format.  
Low = complementary offset binary,  
High = 2s complement.  
Input data justification.  
Low = data assumed to be left justi  
fied up to 24 bits in length,  
High = data right justified 16 bits.  
Input data latching.  
encoded input data. (Output current  
rated at 12mA.)  
28: LRCI (I)  
Word clock input.  
14: BCPL (I)  
Low = input data latched on rising  
edge of BCKI. High = input data  
latched on falling edge of BCKI.  
15: SMUTE (I) Soft mute. Low = off, High = on.  
16: DEEMPH(I)De-emphasis filter.  
Pacific Microsonics, Inc.  
32990 Alvarado Niles Road, Suite 910  
Union City , CA 94587  
4
Phone (510) 475-8000  
Fax (510) 475-8005  
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