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PIC16F877T-20PQ 参数 Datasheet PDF下载

PIC16F877T-20PQ图片预览
型号: PIC16F877T-20PQ
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器\n [8-Bit Microcontroller ]
分类和应用: 微控制器
文件页数/大小: 200 页 / 3338 K
品牌: ETC [ ETC ]
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PIC16F87X  
2
9.2.12 I C MASTER MODE RECEPTION  
Master mode reception is enabled by programming the  
receive enable bit, RCEN (SSPCON2<3>).  
Note: The SSP module must be in an IDLE  
STATE before the RCEN bit is set or the  
RCEN bit will be disregarded.  
The baud rate generator begins counting, and on each  
rollover, the state of the SCL pin changes (high to  
low/low to high), and data is shifted into the SSPSR.  
After the falling edge of the eighth clock, the receive  
enable flag is automatically cleared, the contents of the  
SSPSR are loaded into the SSPBUF, the BF flag is set,  
the SSPIF is set, and the baud rate generator is sus-  
pended from counting, holding SCL low. The SSP is  
now in IDLE state, awaiting the next command. When  
the buffer is read by the CPU, the BF flag is automati-  
cally cleared. The user can then send an acknowledge  
bit at the end of reception, by setting the acknowledge  
sequence enable bit, ACKEN (SSPCON2<4>).  
9.2.12.1 BF STATUS FLAG  
In receive operation, BF is set when an address or data  
byte is loaded into SSPBUF from SSPSR. It is cleared  
when SSPBUF is read.  
9.2.12.2 SSPOV STATUS FLAG  
In receive operation, SSPOV is set when 8 bits are  
received into the SSPSR, and the BF flag is already set  
from a previous reception.  
9.2.12.3 WCOL STATUS FLAG  
If the user writes the SSPBUF when a receive is  
already in progress (i.e. SSPSR is still shifting in a data  
byte), then WCOL is set and the contents of the buffer  
are unchanged (the write doesn’t occur).  
1999 Microchip Technology Inc.  
DS30292B-page 83  
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