57
CY7C455
CY7C456
CY7C457
512 x 18, 1K x 18, and 2K x 18 Cascadable
Clocked FIFOs with Programmable Flags
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 512 x 18 (CY7C455)
• 1,024 x 18 (CY7C456)
• 2,048 x 18 (CY7C457)
• 0.65 micron CMOS for optimum speed/power
• High-speed 83-MHz operation (12 ns read/write cycle
time)
• Low power — I
CC
=90 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL compatible
• Retransmit function
• Parity generation/checking
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 52-pin PLCC and 52-pin PQFP
Functional Description
The CY7C455, CY7C456, and CY7C457 are high-speed,
low-power, first-in first-out (FIFO) memories with clocked read
and write interfaces. All are 18 bits wide. The CY7C455 has a
512-word memory array, the CY7C456 has a 1,024-word
memory array, and the CY7C457 has a 2,048-word memory
array. The CY7C455, CY7C456, and CY7C457 can be cas-
caded to increase FIFO depth. Programmable features in-
clude Almost Full/Empty flags and generation/checking of par-
ity. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multi-
processor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW).
Logic Block Diagram
D
0 – 17
Pin Configurations
PLCC
Top View
V
CC
V
CC
(N)
D
3
D
4
D
5
D
6
D
7
D
8
V
SS
D
9
D
10
D
11
D
12
INPUT
REGISTER
CKW
ENW
PARITY
WRITE
CONTROL
FLAG/PARITY
PROGRAM
REGISTER
7 6 5 4 3 2 1 52 51 50 49 48 47
D
2
D
1
D
0
XI
HF
ENW
E/F
CKW
PAFE/XO
HF
E/F
XO/PAFE
Q
0
Q
1
Q
2
Q
3
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
29 30 31 32 33
Q
11
Q
12
Q
13
Q
14
c455-2
D
13
D
14
D
15
D
16
D
17
FL/RT
MR
CKR
ENR
OE
Q
17
/PG2/PE2
Q
16
Q
15
FLAG
LOGIC
RAM
ARRAY
512 x 18
1024 x 18
2048 x 18
7C455
7C456
7C457
WRITE
POINTER
MR
FL/RT
XI
RESET
LOGIC
READ
POINTER
21 22 23 24 25 26 27 28
Q
4
Q
5
Q
6
Q
7
Q
8
/PG1/PE1
V
SS
c455-1
EXPANSION
LOGIC
THREE–STATE
OUTPUT REGISTER
OE
Q
0 – 7
, Q
8
/PG1/PE1
Q
9– 16
, Q17/PG2/PE2
READ
CONTROL
RETRANSMIT
LOGIC
CKR
ENR
Cypress Semiconductor Corporation
Document #: 38-06003 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 3, 1997
V
SS
(N)
Q
9
Q
10
ETC [ ETC ]
