CY7C455
CY7C456
CY7C457
Switching Characteristics
Over the Operating Range
[13]
7C455/6/7– 7C455/6/7– 7C455/6/7–
12
14
20
Parameter
t
CKW
t
CKR
t
CKH
t
CKL
t
A
t
OH
t
FH
t
SD
t
HD
t
SEN
t
HEN
t
OE
t
OLZ[7, 14]
t
OHZ[7, 14]
t
PG
t
PE
t
FD
t
SKEW1[15]
t
SKEW2[16]
t
PMR
t
SCMR
t
OHMR
t
MRR
t
MRF
t
AMR
t
SMRP
t
HMRP
t
FTP
t
AP
t
OHP
t
PRT
t
RTR
Write Clock Cycle
Read Clock Cycle
Clock HIGH
Clock LOW
Data Access Time
Previous Output Data Hold After Read HIGH
Previous Flag Hold After Read/Write HIGH
Data Set-Up
Data Hold
Enable Set-Up
Enable Hold
OE LOW to Output Data Valid
OE LOW to Output Data in Low Z
OE HIGH to Output Data in High Z
Read HIGH to Parity Generation
Read HIGH to Parity Error Flag
Flag Delay
Opposite Clock After Clock
Opposite Clock Before Clock
Master Reset Pulse Width (MR LOW)
Last Valid Clock LOW Set-Up to MR LOW
Data Hold From MR LOW
Master Reset Recovery
(MR HIGH Set-Up to First Enabled Write/Read)
MR HIGH to Flags Valid
MR HIGH to Data Outputs LOW
Program Mode—MR LOW Set-Up
Program Mode—MR LOW Hold
Program Mode—Write HIGH to Read HIGH
Program Mode—Data Access Time
Program Mode—Data Hold Time from MR HIGH
Retransmit Pulse Width
Retransmit Recovery Time
0
12
12
12
9
12
12
0
14
14
0
12
14
0
0
12
12
12
14
10
14
14
0
20
20
0
9
9
9
9
0
14
14
0
0
14
14
14
20
15
20
20
0
30
30
0
0
4
0
4
0
9
0
10
10
10
10
0
20
20
0
0
20
20
20
30
20
30
30
Description
12
12
5
5
9
0
0
5
0
5
0
10
0
15
15
15
15
0
30
30
0
0
30
30
30
14
14
6.5
6.5
10
0
0
6
0
6
0
15
0
20
20
20
20
20
20
9
9
15
0
0
7
0
7
0
20
7C455/6/7–
30
Unit
ns
ns
ns
ns
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
12
12
Min. Max. Min. Max. Min. Max. Min. Max.
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and
Waveforms and capacitance as in notes 8 and 9, unless otherwise specified.
14. At any given temperature and voltage condition, t
OLZ
is greater than t
OHZ
for any given device.
15. t
SKEW1
is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle
(for purposes of flag update). If the opposite clock occurs less than t
SKEW1
after the clock, the decision of whether or not to include the
opposite clock in the current clock cycle is arbitrary.
Note:
The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is
the opposite clock for Empty and Almost Empty flags, CKR is the opposite clock for the Almost Full, Half Full, and Full flags. The clock is the signal
to which a flag is synchronized; i.e., CKW is the clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags.
16. t
SKEW2
is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than t
SKEW2
before the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. See Note 15 for definition of clock and opposite clock.
Document #: 38-06003 Rev. **
Page 6 of 23
ETC [ ETC ]
