CY7C455
CY7C456
CY7C457
Switching Waveforms
(continued)
Read to Empty Timing Diagram
COUNT
3
2
[21, 24, 25]
1
0
1
1 (NO CHANGE)
LATENT CYCLE
0
CKR
ENR
R1
ENABLED
READ
R2
ENABLED
READ
R3
ENABLED
READ
R4
FLAG
UPDATE
READ
R5
ENABLED
READ
t
SKEW1
CKW
ENW
E/F
LOW
t
SKEW2
W1
ENABLED
WRITE
t
FD
t
FD
t
FD
c455-12
Read to Empty Timing Diagram with Free-RunningClocks
COUNT
1
0
R1
ENABLED
READ
R2
IGNORED
READ
1
[21, 22, 23, 24]
LATENT CYCLE
0
R5
ENABLED
READ
R6
IGNORED
READ
CKR
R3
IGNORED
READ
t
SKEW2
ENR
t
SKEW1
CKW
W1
W2
R4
FLAG
UPDATE
READ
t
SKEW2
W3
ENABLED
WRITE
W4
W5
W6
ENW
HF
HIGH
t
FD
E/F
PAFE
LOW
t
FD
t
FD
c455-11
Notes:
21. “Count” is the number of words in the FIFO.
22. The FIFO is assumed to be programmed with P>0 (i.e., PAFE does not transition at Empty or Full).
23. R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write after empty, occurs
less than t
SKEW2
before R3. Therefore, the FIFO still appears empty when R3 occurs. Because W3 occurs greater than t
SKEW2
before R4, R4 includes
W3 in the flag update.
24. CKR is clock and CKW is opposite clock.
25. R3 updates the flag to the Empty state by asserting E/F. Because W1 occurs greater than t
SKEW1
after R3, R3 does not recognize W1 when updating
flag status. But because W1 occurs t
SKEW2
before R4, R4 includes W1 in the flag update and, therefore, updates FIFO to Almost Empty state. It is
important to note that R4 is a latent cycle; i.e., it only updates the flag status regardless of the state of ENR. It does not change the count or the
FIFO’s data outputs.
Document #: 38-06003 Rev. **
Page 9 of 23
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