23
IPM Dead Time and
Propagation Delay
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in Figure
25) are off. Any overlap in Q1
and Q2 conduction will result in
large currents flowing through
the power devices between the
high and low voltage motor rails.
Specifications. (Discussion
applies to HCPL-3120, HCPL-
J312, and HCNW3120)
The HCPL-3120 includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
I
LED1
I
LED1
V
OUT1
V
OUT1
Q1 ON
Q1 ON
Q1 OFF
Q2 ON
Q1 OFF
Q2 ON
Q2 OFF
V
OUT2
Q2 OFF
V
OUT2
I
LED2
I
LED2
t
PHL MIN
t
PHL MAX
t
PHL MAX
t
PLH MIN
t
PLH
MIN
PDD* MAX = (t - t
)
= t
- t
PHL PLH MAX
PHL MAX PLH MIN
t
PLH MAX
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
(t
t
)
PHL- PLH MAX
PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
Figure 35. Minimum LED Skew for Zero Dead Time.
= (t
= (t
- t
) + (t )
- t
PHL MAX PHL MIN
PLH MAX PLH MIN
- t
PHL MAX PLH MIN
) – (t
- t )
PHL MIN PLH MAX
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 36. Waveforms for Dead Time.
HCNW3120
(mW)
HCPL-3120 OPTION 060/HCPL-J312
1000
800
700
600
500
400
300
P
I
(mW)
P
I
S
S
900
800
700
600
500
400
300
200
(mA)
(mA) FOR HCPL-3120
S
S
OPTION 060
I
(mA) FOR HCPL-J312
S
200
100
0
100
0
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
0
25
50 75 100 125 150 175
T
T
– CASE TEMPERATURE – °C
S
S
Figure 37. Thermal Derating Curve, Dependence of Safety Limiting Value
with Case Temperature per VDE 0884.
ETC [ ETC ]
