PIC12F510/16F506
FIGURE 5-2:
BLOCK DIAGRAM OF
GP0/RB0 AND GP1/RB1
FIGURE 5-3:
BLOCK DIAGRAM OF
GP3/RB3 (With Weak
Pull-up And Wake-up On
Change)
GPPU
RBPU
GPPU
RBPU
Data
MCLRE
Bus
D
Q
Q
Data
Latch
(1)
I/O Pin
WR
Port
CK
Reset
W
Reg
(1)
I/O Pin
D
Q
Q
TRIS
Latch
TRIS ‘f’
CK
Data Bus
RD Port
Q
Reset
ADC pin Ebl
D
COMP pin Ebl
CK
RD Port
Mis-match
Q
D
CK
Mis-Match
ADC
COMP
Note 1: I/O pins have protection diodes to VDD and
Note 1: GP3/MCLR pin has a protection diode to VSS
VSS.
only.
DS41268B-page 28
Preliminary
© 2006 Microchip Technology Inc.
ETC [ ETC ]
