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12F5101 参数 Datasheet PDF下载

12F5101图片预览
型号: 12F5101
PDF下载: 下载PDF文件 查看货源
内容描述: - 12号的铝制车身绘( RAL 7032 ) []
分类和应用:
文件页数/大小: 114 页 / 1604 K
品牌: ETC [ ETC ]
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PIC12F510/16F506  
EXAMPLE 4-1:  
HOW TO CLEAR RAM  
USING INDIRECT  
ADDRESSING  
4.8  
Indirect Data Addressing: INDF  
and FSR Registers  
The INDF register is not a physical register. Addressing  
INDF actually addresses the register whose address is  
contained in the FSR register (FSR is a pointer). This is  
indirect addressing.  
MOVLW  
MOVWF  
0x10  
;initialize pointer  
;to RAM  
FSR  
NEXT  
CLRF  
INCF  
BTFSC  
GOTO  
INDF  
FSR,F  
FSR,4  
NEXT  
;clear INDF register  
;inc pointer  
;all done?  
4.8.1  
INDIRECT ADDRESSING EXAMPLE  
;NO, clear next  
CONTINUE  
• Register file 07 contains the value 10h  
• Register file 08 contains the value 0Ah  
• Load the value 07 into the FSR register  
:
:
;YES, continue  
• A read of the INDF register will return the value  
of 10h  
The FSR is a 5-bit wide register. It is used in conjunc-  
tion with the INDF register to indirectly address the data  
memory area.  
• Increment the value of the FSR register by one  
(FSR = 08)  
The FSR<4:0> bits are used to select data memory  
addresses 00h to 1Fh.  
• A read of the INDR register now will return the  
value of 0Ah.  
PIC16F506 – Uses FSR<6:5>. Selects from Bank 0 to  
Bank 3. FSR<7> is unimplemented, read as ‘1’.  
Reading INDF itself indirectly (FSR = 0) will produce  
00h. Writing to the INDF register indirectly results in a  
no operation (although Status bits may be affected).  
A simple program to clear RAM locations 10h-1Fh  
using indirect addressing is shown in Example 4-1.  
PIC12F510 – Uses FSR<5>. Selects from Bank 0 to  
Bank 1. FSR<7:6> are unimplemented, read as ‘11’.  
FIGURE 4-5:  
DIRECT/INDIRECT ADDRESSING (PIC12F510)  
Direct Addressing  
(opcode)  
Indirect Addressing  
(FSR)  
(FSR)  
4
3
2
1
0
5
3
2
1
0
6
4
5
6
bank select  
bank  
select  
location select  
location select  
00  
01  
00h  
Addresses map back to  
addresses in Bank 0.  
Data  
Memory  
0Fh  
10h  
(1)  
1Fh  
3Fh  
Bank 1  
Bank 0  
Note 1: For register map detail, see Figure 4-2.  
DS41268B-page 24  
Preliminary  
© 2006 Microchip Technology Inc.  
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