PIC12F510/16F506
FIGURE 3-2:
PIC16F506 SERIES BLOCK DIAGRAM
10
8
PORTB
Data Bus
Program Counter
RB0/ICSPDAT
RB1/ICSPCLK
RB2
RB3
RB4
Flash
1K x 12
Program
Memory
RAM
67 bytes
File
Registers
STACK 1
STACK 2
RB5
Program
Bus
10
RAM Addr
9
PORTC
Addr MUX
Instruction Reg
RC0
RC1
RC2
RC3
RC4
RC5
Indirect
Addr
5
Direct Addr
5-7
FSR Reg
STATUS Reg
8
C1IN+
Comparator 1
C1IN-
C1OUT
3
MUX
Device Reset
Timer
VREF
Instruction
Decode &
Control
Power-on
Reset
C2IN+
C2IN-
ALU
Comparator 2
8
Watchdog
Timer
C2OUT
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
W Reg
Internal RC
Clock
CVREF
CVREF
CVREF
Timer0
AN0
AN1
AN2
VDD, VSS
MCLR
8-bit ADC
VREF
T0CKI
DS41268B-page 12
Preliminary
© 2006 Microchip Technology Inc.
ETC [ ETC ]
