TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
22 Cross Connect (XC) Block Functional Description (continued)
22.6.6 Framer System Interface
The framer system interface FRM_TS/FRM_RS consists of bundles of data, clock, and/or sync/miscellany, that
may only be connected to the device external I/O pins. The system interface operates as the parallel system bus
(PSB), concentration highway (CHI), or network serial multiplexed interface (NSMI). Note that not all pins are used
in these configurations. The user should exercise caution in mixing the usage of the external pins between system
interface TS/RS usage and any other use.
Two register bits, XC_SI_CHI and XC_SYNC_FOR_DATA (Table 461 on page 327), and a group of seven 2-bit
parameters XC_CHI_MODE[1—7][1:0] (Table 462 on page 327) are used to assist with the configuration of the
system interface.
22.6.7 Framer System Interface—PSB
The framer system interface is configured for the parallel system bus as depicted in Figure 87. Program bit
XC_SI_CHI = 1 to select the PSB mode, and bit XC_SYNC_FOR_DATA = 1 to allow the connecting of transmit sys-
tem data outputs to the LINETXSYNC[1—29] pins. The programming of the XC_CHI_MODE[1—7][1:0] bits is not
required.
The PSB configuration is completed by programming appropriate source IDs into the XC_RS_D[1—28][7:0]
(Table 469 on page 329) and XC_SYNC[1—29] (Table 477 on page 332) bytes of the XC_FRS_SRC[1—14]
(Table 469) and XC_PINS_SRC[1—14] (Table 477 on page 332) XC1 crosspoint configuration registers.
XC
FRAMER SYSTEM INTERFACE
FRM_TS/FRM_RS
EXTERNAL I/O
AS PSB
XC_SI_CHI = 1
XC_SYNC_FOR_DATA = 1
XC_CHI_MODE[1—7][1:0] = 00 XC_SYNC[1—29][7:0]
Σ
LINETXSYNC[16—13]
LINETXSYNC[4—1]
TS_D[16—1]
Σ
XC_RS_D[1—28][7:0]
RS_D[16—1]
LINERXSYNC[16—1]
LINETXCLK29
TS_GCLK
TS_GFS
LINETXSYNC29
LINERXCLK29
RS_GCLK
LINERXSYNC29
LINERXDATA29
RS_GFS
RS_GTCLK
XC1
5-9185(F)r.2
Figure 87. Framer System Interface—Parallel System Bus (PSB)
22.6.8 Framer System Interface—CHI
The framer system interface is configured for CHI operation as shown in Figure 88. Program bit XC_SI_CHI = 0
(Table 461 on page 327) to select the CHI mode, and bit XC_SYNC_FOR_DATA = 1 (Table 461) to allow the con-
necting of transmit system data outputs to the LINETXSYNC[1—29] pins.
562
Agere Systems Inc.
ETC [ ETC ]
