Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
22 Cross Connect (XC) Block Functional Description (continued)
The cross connect block supports DS2 mapping to/from the M13 MUX, TPG/TPM, and external pin I/O. Here, the
available sources are the M12 MUX or the M23 deMUX, a set of external I/O pins, or the test-pattern generator.
The DS2 crosspoint’s connectivity is determined by a smaller set of source 2 identifiers (SOURCE2_IDs), as
defined in the following table (covering registers XC2_M23_SRC[1—7] (Table 472 on page 330) and
XC2_TPM_SRC (Table 473 on page 331)):
Bit
7
6
5
4
3
2
1
0
SOURCE2_ID
0
SOURCE2_BLOCK[1:0]
CHANNEL2_ID[4:0]
The SOURCE2_BLOCK is defined as follows:
Index
00
Block2 Identifier
TPG (DS2 Test-Pattern Generator)
M13:M12 MUX
01
10
M13:M23 DeMUX
11
External I/O
The CHANNEL2_ID typically ranges from 1 to 7. For test data from the TPG, the SOURCE2_BLOCK is set to 0
and the CHANNEL2_ID value four represents the DS2 test pattern. For DS2 signals routed from external pins to
the input of M23 MUX or TPM, the CHANNEL2_ID can range from 1 to 29. The above DS2 source ID definition
covers registers beginning with XC2.
Note: For certain DS2 signals routed to external pins, the XC1 cross connect is used and a special SOURCE_ID
(block 0) is programmed:
Bit
7
6
5
4
3
2
1
0
SOURCE2_ID
0
0
0
CHANNEL2_ID[4:0]
The SOURCE2_ID is defined as in Table 627 on page 558 to Table 629 on page 559. The user must ensure con-
sistency between the use of M13 vs. M12/M23 channels and external I/O channels.
22.7.1 M13 DS2 Interface (DS2 Cross Connect)
The DS2 full split access results in four sets of DS2 signals that can be routed through cross connect, essentially
providing access to the path between the seven M12 MUX/deMUXs and the M23 MUX/deMUX.
22.7.2 M12 MUX (Transmit Path)
The M12 MUX assembles three E1s or four DS1s into a DS2. The DS2 output data is clocked out by an external
DS2 rate clock as shown in Figure 90.
The DS2 rate clock is routed from an external pin, LINETXSYNC[14—8], through the cross connect to the M12, by
programming the XC2_DS2M12CLK[1—7][7:0] (Table 471 on page 330) bytes in the DS2 cross connect registers
XC2_M12_SRC[1—7] (Table 471) with a source2 ID = 11 (external I/O) and a channel select of 1 to 7. The channel
select value of 1 to 7 selects the clock from pins LINETXSYNC[8] to LINETXSYNC[14], respectively.
The DS2 data is routed through the DS1 cross connect to the external pins, LINETXSYNC[7—1], by programming
the XC_SYNC[1—29] (Table 477 on page 332) bytes in the XC_PINS_SRC[1—14] DS1 cross connect registers
with a source ID = 000 and a channel select as defined in Table 628 on page 558. A channel select value of 9 to 15
selects the external pin LINETXSYNC[1] to LINETXSYNC[7], respectively.
Agere Systems Inc.
565
ETC [ ETC ]
