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TMXF281553BAL-3C-DB 参数 Datasheet PDF下载

TMXF281553BAL-3C-DB图片预览
型号: TMXF281553BAL-3C-DB
PDF下载: 下载PDF文件 查看货源
内容描述: 电信/数据通信\n [Telecomm/Datacomm ]
分类和应用: 电信数据通信
文件页数/大小: 784 页 / 10078 K
品牌: ETC [ ETC ]
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TMXF28155 Supermapper  
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1  
Data Sheet  
June 2002  
22 Cross Connect (XC) Block Functional Description (continued)  
XC_MDS1DATA[1—28][7:0]  
M13  
EXT I/O—SOURCE_ID = 001  
CHANNEL_ID = 1 TO 29 —PIN SELECT  
BUNDLED SIGNALS  
EXTERNAL I/O  
LINERXDATA  
XC  
M13_DS1_DATA  
M13_DS1_CLOCK  
M13_DS1_STUFF  
REQUEST  
LINERXSYNC  
LINERXCLK  
M13_DS1_CLOCK  
(DEMUX FROM M13)  
XC_ALCO[1—29][7:0]  
SOURCE_ID = 011  
CHANNEL_ID FROM 1 TO 29  
REGISTER BIT XC_DS1ALCOEN  
0 = DS1 EXTERNAL CLOCK IN  
1 = DS1 M13 DEMUX CLOCK OUT  
XC1  
5-9183(F)r.2  
Figure 85. DS1E1 External I/O to M13  
22.6.3 VT Mapper DS1/E1 Interface  
The user configures the VT mapper DS1/E1 connections from the crosspoint by loading the appropriate  
SOURCE_IDs into the VT mapper crosspoint configuration registers.  
The user may connect any valid DS1 or E1 signal bundle from the M13 MUX, framer, external I/O, TPG, or DJA  
blocks to any VT mapper input. Each of the 28 possible DS1 or 21 possible E1 inputs may be assigned an XC1  
source ID for the corresponding XC_VDATA[1—28][7:0] (Table 466 on page 329) byte in the XC_VT_SRC[1—14]  
configuration registers. The user must ensure the consistency of the designation of DS1(J1) vs. E1 channels and  
block interface parameters.  
The cross connect block automatically supports independent signal paths for remote alarm indication (RAI), alarm  
indicator signal (AIS), frame sync (byte-synchronous mode only), and signaling (out-of-band signaling) on chan-  
nels between the VT mapper and the framer.  
22.6.4 Digital Jitter Attenuator (DJA) Interface  
The DJA block consists of up to 28 DS1 jitter attenuator channels or up to 21 E1 jitter attenuation channels. The  
DS1 or E1 channels are cross connected from the VT mapper, M13 MUX, framer, external I/O interface, or test  
interface, and the DJA outputs are returned to the crosspoint switch for cross connect to the destination. Test sig-  
nals from the TPG will not require jitter attenuation, although this capability exits. The crosspoint cannot chain jitter  
attenuators together serially (that is, DJA to DJA paths are not supported).  
The user configures the DJA DS1(E1) outputs from the crosspoint by loading the appropriate SOURCE_IDs into  
the DJA crosspoint configuration registers.  
The user may connect any valid DS1 or E1 signal bundle from the external I/O pin, M13, VT mapper, framer, or  
TPG blocks to any DJA input. Each of the 28 possible DS1 (J1) or 21 possible E1 inputs may be assigned an XC1  
source ID for the corresponding XC_JDATA[1—28][7:0] (Table 467 on page 329) byte in the XC_DJA_SRC[1—14]  
configuration registers. The user must ensure the consistency of the designation of DS1(J1) vs. E1 channels.  
The cross connect is provided with DS1 and E1 reference clocks from the DJA block. These 1X clocks are derived  
from external AIS clock inputs, and are made available to the test-pattern generator block for use as the test-pat-  
tern source clocks. The DJA block is responsible for the correct assignment of reference clocks to jitter attenuation  
channels.  
When a channel from the VT mapper is cross connected to a DJA channel, the bundled signals include receive  
pointer adjustment information. For all other sources, the pointer adjustment signal is not required and is disabled.  
560  
Agere Systems Inc.