Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(continued)
Table 629. Special XC_ALCO Source IDs for Source Block = 0
Blk Ch.
0
0
1
2
3
4
5
6
7
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Blk Ch.
0
8
9
10
11
12
13
14
15
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Blk Ch.
0 16
17
18
19
20
21
22
23
Description
Reserved
M23_DS2CLKO_1
M23_DS2CLKO_2
M23_DS2CLKO_3
M23_DS2CLKO_4
M23_DS2CLKO_5
M23_DS2CLKO_6
M23_DS2CLKO_7
Blk Ch.
0 24
25
26
27
28
29
30
31
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Since register information is generally not shared between other blocks and the XC block, the user is responsible
for correct programming of the crosspoint. That is, the user must ensure the consistency of the designation of DS1
(or J1) vs. E1 channels. Also, in the configuration of the M13 MUX, the user must ensure the correct allocation of
DS1/E1 vs. DS2 channels, as well as coordinating the designation or ordering of DS2 channels within the DS3 (in
the independent M12 MUX mode).
22.6 Notes on the DS1 Cross Connect
22.6.1 DS1/E1 TPG
DS1 test signals are available at any XC1 output channel by specifying value 000 in the SOURCE_ID field. The
CHANNEL_ID field is set to zero for standard DS1 test-data patterns and one for DS1 (framed) idle data.
E1 test signals are available at any XC1 output channel by specifying value 0 in the SOURCE_ID field. The
CHANNEL_ID field is set to two for standard E1 test-data patterns.
22.6.2 M13 DS1/E1 Interface
The user configures the M13 DS1(E1) connections from the crosspoint by loading the appropriate SOURCE_IDs
into the M13 crosspoint configuration registers.
The user may connect any valid DS1 or E1 (XC1 input) signal bundle from the framer, VT mapper, external I/O,
TPG, or DJA to any M13 input configured as a DS1 or E1 input. Each of the 28 possible M13 (DS1) or 21 possible
E1(J1) inputs may be assigned an XC1 source ID for the corresponding XC_MDS1DATA[1—28][7:0] (Table
byte in the XC_M13_SRC[1—14] configuration registers. Since register information is not shared
between the M13 block and the XC1 block, the user is responsible for correct programming of the crosspoint by
ensuring the consistency of the designation of M13 vs. M12/M23 channels, as well as coordinating the designation
of DS1 vs. E1(J1) channels.
The cross connect block automatically supports independent signal paths for alarm indicator signal (AIS) on chan-
nels between the M13 and the framer.
The XC1 supports a mode where the M13 block provides the DS1/E1 clock out for data to be multiplexed in from
the external I/O device pins, as depicted in
DS1/E1 low clock-out mode is enabled with register bit
XC_DS1ALCOEN = 1 (Table
In this mode, the appropriate DS1 or E1 level clock is routed to the
LINERXCLK[1—29] device pin by programming the corresponding XC_ALCO[1—29][7:0] byte in registers
XC_ALCO_SRC[1—15] with the M13 SOURCE_ID = 011 and the channel ID of the selected M13 channel. The
LINERXCLK[1—29] clock output is used to clock in data from the associated LINERXDATA[1—29] device pin and
a stuff request input from the LINERXSYNC[1—29] device pin. In this mode, the M12 stuff time is determined
externally.
Agere Systems Inc.
559
ETC [ ETC ]
