Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
17 TMUX Functional Description (continued)
17.5.1 Input Clock and Loss-of-Signal Monitoring
The TMUX detects and reports the loss of the 155 MHz input clock for the STS-3 mode and the loss of the
51.84 MHz clock for the STS-1 mode with register bits TMUX_RHSILOC—state (Table 101, starting on page 94),
TMUX_RHSILOCD—delta state (Table 101, starting on page 94), and TMUX_RHSILOCM—interrupt mask
(Table 101, starting on page 94). LOC is determined by a stuck high or stuck low for a time greater than 10 µs and
uses the microprocessor clock as its reference.
The TMUX will detect and report a loss-of-signal condition with register bits TMUX_RHSLOS—state (Table 101 on
page 94), TMUX_RHSLOSD—delta state (Table 101, starting on page 94), TMUX_RHSLOSM—interrupt mask
(Table 96 on page 90), by monitoring the external input signal pin, LOSEXT (pin AE5), or detecting a continuous
all-zeros/ones pattern for 51.44 ns to 105 µs in 51.44 ns steps before data is descrambled. The detection time is
determined by the value programmed in register bits, TMUX_LOSDETCNT[10:0] (Table 107 on page 99). The
LOS state will clear after reception of two consecutive receive frames with the correct framing pattern spaced 125
µs apart without an incoming LOS all-zeros/ones pattern. This recovery applies to both internal and external LOS
failure causes.
17.5.2 High-Speed Loopback Select Logic
The device can be configured to loop back the transmit STS-3/STM-1 (AU-4) TMUX_THS2RHSLB = 1 (Table 103
on page 96) or accept the local STS-3/STM-1 (AU-4) signal TMUX_THS2RHSLB = 0.
17.5.3 Frame Alignment—STS-3/STM-1 (AU-4) Framing or STS-1 Framing
The device will frame on the incoming signal. The state of the framer, out of frame (OOF) (register bit
TMUX_RHSOOF; see Table 101 on page 94) as well as any changes to this state (register bits
TMUX_RHSOOFD—delta state; see Table 101, starting on page 94 and TMUX_RHSOOFM—interrupt mask; see
Table 96 on page 90) will be reported.
The 32-bit (A1-2, A1-3, A2-1, and A2-2) framing pattern will be used in the frame detection for the
STS-3/STM-1 case and a 16-bit pattern will be used for the STS-1 case. The device will be considered out of frame
until two successive framing patterns separated in time by 125 µs occur without framing byte errors.
The device will be considered in frame until five successive frames, separated in time by 125 µs, occur with errored
framing patterns. If the framer transitions to the out of frame state, the framer will remain synchronized to the last
known frame boundary or the latest detected unerrored framing pattern.
A loss of frame (LOF) (register bit TMUX_RHSLOF; see Table 101 on page 94) state bit as well as any changes to
this state (register bits TMUX_RHSLOFD—delta state; see Table 101, starting on page 94, TMUX_RHSLOFM—
interrupt mask; see Table 96 on page 90) will be reported. These state and mask and delta bits are the same for
both types of input data, STS-3/STM-1 or STS-1.
The device will be considered in the LOF state when an OOF condition persists for 24 consecutive frames (3 ms).
The device will transition out of the LOF state after receiving 24 consecutive frames with the correct framing pat-
terns spaced 125 µs apart and the OOF condition is clear.
17.5.4 B1 BIP-8 Check
A BIP-8 even parity will be computed over all the incoming bits of the STS-3/STM-1 frame (STS-1 frame in STS-1
mode), which are scrambled (except for the bits in the A1, A2, and J0/Z0 bytes) and compared to the B1 byte
received in the next frame.
The total number of B1 BIP-8 bit errors (raw count), or block errors (as determined by register bit
TMUX_BITBLKB1; see Table 105 on page 97), are counted. Upon the assertion of the performance monitor con-
trol signal as configured in the microprocessor interface block, the raw count will be reset to zero and the value
transferred to a 16-bit counter for B1 error counts B1ECNT[15:0] (Table 134 on page 120).
Agere Systems Inc.
375
ETC [ ETC ]
