TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
17 TMUX Functional Description (continued)
Any change to TMUX_RLAISMON will be reported in TMUX_RLAISMOND (Table 92, starting on page 81) and the
interrupt can be masked using TMUX_RLAISMONM (Table 96 on page 90).
The TMUX monitors for a remote defect indication (RDI-L/MS-RDI) condition in the K2[2:0] bits (K2[2:0] = 110). A
line RDI condition will be detected and TMUX_RLRDIMON (Table 101 on page 94) will be set to 1 after a number
of consecutive occurrences of RDI as determined by the value in TMUX_CNTDK2[3:0]. Once set, RDI-L will be
cleared after a number of consecutive frames of no RDI as determined by this same value programmed in
TMUX_CNTDK2[3:0]. Any change to TMUX_RLRDIMON will be reported in TMUX_RLRDIMOND (Table 92, start-
ing on page 81), and the interrupt can be masked using TMUX_RLRDIMONM (Table 96 on page 90). This contin-
uous N-times detection counter will be reset to 0 upon the transition of the framer into the out of frame state.
17.5.11 M1 REI-L Detect
One byte (M1) is allocated for use as a line remote error indication function (REI-L). For STS-3/STM-1 signals, all
eight bits of the M1 byte are allocated for REI-L information. The REI-L value reflects the error count detected by
the line terminating equipment (LTE) (using the line BIP-8 code) back to its peer LTE. For STS-3/STM-1 signals,
the value of the error count can be up to 24. A value of 25 and above will be interpreted as no errors. If
TMUX_R_M1_BIT7 (Table 106 on page 98) is 1, then the most significant bit of the byte is ignored.
The TMUX allows access to the accumulated M1-REI errored bit count from the M1 byte via TMUX_M1ECNT[17:0]
(Table 136 on page 121). The counter will count in bit or block mode, depending upon the value of
TMUX_BITBLKM1 (Table 104 on page 96). At the selected performance monitor (PM) interval, the value of the
internal running raw counter is placed into a holding register, TMUX_M1ECNT[17:0], and then cleared. Depending
on the value of SMPR_SAT_ROLLOVER (Table 77 on page 70) in the microprocessor interface, the internal
counter will either roll over or saturate at its maximum value until cleared.
17.5.12 Sync Status Monitor
The S1 byte is allocated for synchronization status. S1 bits [7:4] are used to convey a 4-bit code of which only six
patterns are defined, with the remaining codes reserved for quality levels defined by individual administrations.
The S1 byte can be monitored in two modes: as an entire 8-bit word or as one 4-bit nibble (bits [7:4]), as pro-
grammed by TMUX_S1MODE4 (Table 105 on page 97).
■ TMUX_S1MODE4 = 0. The associated state, delta, and mask registers are TMUX_RS1MON[7:0] (Table 113 on
page 102), TMUX_RS1MOND (Table 92, starting on page 81), and TMUX_RS1MONM (Table 96 on page 90),
respectively.
■ TMUX_S1MODE4 = 1. The associated state, delta, and mask registers are TMUX_RS1MON[7:4],
TMUX_RS1MOND, and TMUX_RS1MONM.
A new value will be detected after a programmed number of consecutive occurrences of a consistent new value in
the incoming S1 byte as determine by the value in TMUX_CNTDS1[3:0] (Table 108 on page 100). A maskable
event, TMUX_RS1BABE (Table 92, starting on page 81), is set if a programmed number of consecutive frames
pass without a validated message occurring as determined by the value in TMUX_CNTDS1FRAME[3:0]
(Table 108 on page 100).
In 8-bit mode, the entire value is monitored for an inconsistent value, while in 4-bit mode, only the most significant
nibble is monitored for an inconsistent value. This continuous N-times detection counter will be reset to 0 upon the
transition of the framer into the out of frame state.
17.5.13 Receive Transport Overhead Access Channel (RTOAC)
A transport overhead access channel (TOAC) is provided on-chip to drop the transport overhead (TOH) portion of
the incoming SDH or SONET frame. The TOAC channel supports three modes of operation based on the configu-
ration of TMUX_RTOAC_D13MODE and TMUX_RTOAC_D412MODE (Table 127 on page 115).
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Agere Systems Inc.
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