TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
17 TMUX Functional Description (continued)
THSSYNC
RPSSYNC155 (FROM RECEIVE SIDE)
THSC
RPSC155
TPSMUXSEL2
LOC, OOF,
LOF, B2E
TPSC155
TPSD155
LOCAL CLOCK
AND FRAME
GENERATION
B2 ERR
INSERT,
L-REI INS
MSP 1 + 1
PAYLOAD
SWITCH 3
P/S
P/S
TLSCLK52
TLSSYNC52
STS#1
PAIS, UEQ
INSERT
TLSCLK
(19.44 MHz)
STM-1
TOH
INSERT
THSD
3:1
MUX
STS#2
STS#3
TLSDATA[7:0]
TLSPAR
PAIS, UEQ
INSERT
LOGIC
AND
POH
MSP 1 + 1
PAYLOAD
SWITCH 2
INSERT
TOAC
INSERT
PAIS, UEQ
INSERT
TLSSPE
TLSJ0J1V1
TLSV1
TTOACCLKO,
TTOACSYNCO,
TTOACDATI
POAC
INSERT
TPOACCLK,
TPOACSYNC,
TPOACDATA
VTMPR RDI_L, REI_L
TRANSMIT DIRECTION
LINE RDI
LINE REI
VTMPR RDI_P,
REI_P
LOC, OOF,
LOF, B2E
RPSSYNC155
RLSCLK52
PATH RDI
PATH REI
STS#1
STS#2
RLSSYNC52
RLSCLK
(19.44 MHz)
FRAMER,
RPSD155
RPSC155
POINTER
INTERPRETER
S/P, AND
B2 MON,
L-REI MON
RLSDATA[7:0]
1:3
DEMUX
LOGIC
MSP 1 + 1
PAYLOAD
SWITCH 1
RLSPAR
RLSSPE
POH
RHSD
RHSC
FRAMER
AND S/P
MONITOR
STS#3
AUTO_AISO[1—3]
RLSJ0J1V1
RLSV1
TOH
POAC
DROP
MONITOR
TIMING SIGNALS TO TX SIDE
RECEIVE DIRECTION
TOAC
DROP
RTPOACCLK,
RTPOACSYNC,
RTPOACDATA
RTOACCLK,
RTOACSYNC,
RTOACDATA
5-9005(F)r.1
Figure 25. Detailed Block Diagram of the TMUX
372
Agere Systems Inc.
ETC [ ETC ]
