TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
17 TMUX Functional Description (continued)
Table of Contents (continued)
Contents
Page
17.6.19 APS Value and K2 Insert Control Parameters ............................................................................ 400
17.6.20 Criteria for Insert Line RDI .......................................................................................................... 400
17.6.21 Line AIS Generation ................................................................................................................... 400
17.6.22 B2 BIP-8 Calculation and Insert .................................................................................................. 400
17.6.23 F1 Byte Insert ............................................................................................................................. 401
17.6.24 B1 Generate and Error Insert ..................................................................................................... 401
17.6.25 Scrambler ................................................................................................................................... 401
17.6.26 J0 Insert Control ......................................................................................................................... 401
17.6.27 Z0-2, Z0-3 Insert Control ............................................................................................................. 401
17.6.28 A2 Error Insert ............................................................................................................................ 401
Figures
Page
Figure 22. TMUX RTOAC Timing Diagram ...........................................................................................................368
Figure 23. TMUX TTOAC and RTOAC Timing Diagram.......................................................................................371
Figure 24. High-Level TMUX Interconnect ............................................................................................................371
Figure 25. Detailed Block Diagram of the TMUX...................................................................................................372
Figure 26. Receive Direction Functional Block Diagram .......................................................................................373
Figure 27. Pointer Interpretation State Diagram....................................................................................................380
Figure 28. Receive Low-Speed Bus Interface Signals for STS-3/STM-1 Signals .................................................391
Figure 29. Transmit Low-Speed Bus Interface Signals for STS-3/STM-1 Signals ................................................392
Figure 30. Transmit Direction POH and TOH Insertion Diagram ..........................................................................393
Tables
Page
Table 534. Receive TOAC Modes .........................................................................................................................379
Table 535. Transport Overhead Byte Access—Receive Direction ........................................................................379
Table 536. STS Signal Label Defect Conditions....................................................................................................385
Table 537. STS-1 P-REI Interpretation..................................................................................................................386
Table 538. Signal Degrade (SD) Parameters ........................................................................................................388
Table 539. Signal Fail Parameters.........................................................................................................................389
Table 540. Signal Fail or Signal Degrade Recommended Programming Values ..................................................390
Table 541. Path Overhead Byte Access................................................................................................................390
Table 542. Path Overhead Byte Access—Transmit Direction ...............................................................................394
Table 543. TPOAC Control Bits.............................................................................................................................395
Table 544. RDI-P Defects for Enhanced RDI-P Mode...........................................................................................396
Table 545. Transmit TOAC Modes ........................................................................................................................398
Table 546. Transmit Transport Overhead Byte Full Access Mode ........................................................................398
Table 547. TTOAC Control Bits in Full Access Mode............................................................................................399
366
Agere Systems Inc.
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