TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
16 Microprocessor Interface Functional Description (continued)
16.4 MPU Block Diagram
MPCLK
ADDR[19:0]
CSN
INTERNAL
ADDRESS
ADSN
DSN
INTERNAL
DATA
INTERNAL
CONTROL
RWN
DATA[15:0]
DTN
PAR[1:0]
MPMODE
INTN
APS_INTN
5-9039(F)r.2
Figure 19. Microprocessor Interface
16.5 Supermapper Register Address Mapping
Each of the Supermapper’s major functional blocks is selected with an address mapping of the highest-order nib-
ble, device pins ADDR[19:16], and allocated a 16-bit address range, pins ADDR[15:0], as defined in Table 533.
Table 533. Supermapper Register Address Mapping
ADDR[19:16]
0000
Block ID
Block Name
TOP
ADDR
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
0
1
2
3
4
5
6
7
8
0001
M13
0010
VTMPR
SPEMPR
TMUX
XC
0011
0100
0101
0110
TPG
0111
DJA
1000
FRAMER
16.6 Performance Monitoring (PM) Counters Operation
PM counters are error counters or other statistics counters. In general, two internal registers are needed to imple-
ment a PM counter: a running count register (1), maintained by the core logic, which is incremented by 1 every time
an error (or statistics event) happens. At a defined interval, 1 s for example, the content of the running counter is
transferred to a holding register (2), while the running count register is reset to 0 and starts to count anew. The
count holding register holds the data that the microprocessor actually reads.
362
Agere Systems Inc.
ETC [ ETC ]
