Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
16 Microprocessor Interface Functional Description (continued)
PM COUNTER CONTROL
PM COUNTER
RESET
MPU READ HOLDING
REGISTER
PM COUNT EVENT
RUNNING
COUNTER
HOLDING
COUNTER
ENABLE
BUFFERED
MPUCLK
MPU READABLE
(ONE PER BLOCK)
PM COUNT EVENT CLOCK
5-9040(F)r.3
Figure 20. PM Reset Counter
The PM counter control signal controls the transfer and reset of all performance monitoring registers (collecting
events/statistics). The source of this signal is configurable and can come from external pin (PMRST pin T25), an
internal timer, or be controlled by software, depending on the SMPR_PMMODE[1:0] bits (Table 77 on page 70, bits
9:8), described as follows:
SMPR_PMMODE[1:0] = 00, 10: PM counter control is sourced from external pin PMRST.
SMPR_PMMODE[1:0] = 01: PM counter control is sourced from internal 1 s timer. Writing a logic 1 to the
SMPR_PMRESET bit (Table 75 on page 68, bit 8) will reset the timer so that a transition occurs on the internal PM
counter control signal within 10 MPCLK clock cycles. The timer is based on the period of the MPCLK and the pro-
grammed value of the registers in Table 82 on page 73 and Table 83. Once initially reset and synchronized, the
PM counter reset interval is determined by the combined delay of the programmed registers. The device pin,
PMRST, is enabled as an output.
SMPR_PMMODE[1:0] = 11: The PM counter control signal is software controlled. Writing a logic 1 to the
SMPR_PMRESET bit will cause a PM reset within 10 MPCLK cycle times after writing. This pulse will be
100 cycles high and 100 cycles low at the MPCLK frequency. During this 200 cycle time, writing to PM bit will have
no effect. The device pin, PMRST, is enabled as an output.
EXTERNAL
(SMPR_PMMODE[1:0] = 00, 10)
PMRSTI
PMRST (TO BLOCKS)
SMPR_PMRESET
(REGISTER SMPR_GTR bit 8)
SOFTWARE CONTROLLED
(SMPR_PMMODE[1:0] = 11)
PMRSTO
DELAY
MPUCLK
MPUCLK
SMPR_PMRESET_HIGH_COUNT
SMPR_PMRESET_LOW_COUNT
FREE RUNNING
(SMPR_PMMODE[1:0] = 01)
OUTPUT ENABLED
SMPR_PMMODE[1:0] = 01, 11
OUTPUT DISABLED
1/2 SECOND
COUNTERS
SMPR_PMMODE[1:0] = 00, 10
SMPR_PMMODE
(REGISTER SMPR_GCR bits[9:8])
MPU BLOCK
5-9931(F)
Figure 21. PM Reset Signal Generation
Agere Systems Inc.
363
ETC [ ETC ]
