TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
14 Digital Jitter Attenuation Controller Registers (continued)
14.2 Digital Jitter Attenuation Controller Register Map
The register bank architecture of the microprocessor interface is shown in Table 86 on page 75.
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Table 492. DJA Register Map
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
ID and Interrupt Registers (RO)
0x70000
DJA_VERSION
RSVD
DJA_VERSION[2:0]
DJA_ID[7:0]
Page 337
0x70001
0x70002
Delta and Event Parameters (COR/COW)
0x70003
DJA_EVENT1
DJA_EVENT2
RSVD
DJA_G_DS1_ DJA_DS1_DLT DJA_G_E1_ DJA_E1_DLT
DLT DLT
DJA_ESOVFL[28:17]
DJA_ESOVFL[28:17]
Page 337
0x70004
Page 337
DJA_ESOVFL[16:1]
0x70005
Interrupt Mask Parameters for INT Pins (R/W)
0x70006
Page 337
DJA_MASK1
DJA_MASK2
RSVD
DJA_G_DS1_ DJA_DS1_MSK DJA_G_E1_ DJA_E1_MSK
MSK
MSK
0x70007
Page 337
DJA_ESOVFL[16:1]
0x70008
State and Value Parameters (RO)
DJA_E1LOC
0x70009
DJA_STATE1
DJA_STATE2
DJA_G_DS1L DJA_DS1LOC
OC
DJA_G_
E1LOC
Page 338
0x7000A
Page 338
DJA_PTRADJS[16:1]
Control Parameters for PLL Bandwidth and Mode (R/W)
0x7000B
Page 338
DJA_E1GAINH
DJA_E1GAINL
DJA_E1GAIN[26:16]
0x7000C
Page 338
DJA_E1GAIN[15:0]
0x7000D DJA_DS1GAINH
Page 338
DJA_DS1GAINTHR[26:16]
0x7000E DJA_DS1GAINH
Page 338
DJA_DS1GAINTHR[15:0]
DJA_E1SCALE[15:0]
0x7000F
DJA_E1SCALE
Page 338
0x70010 DJA_DS1SCALE
Page 338
DJA_DS1SCALE[15:0]
DJA_BLUECLK
SWITCH
DJA_DS1SCALE[0]
0x70011
DJA_E1PTRH
DJA_E1PTRL
DJA_DS1PTRH
DJA_E1PTRADJCNT[20:16]
Page 339
0x70012
Page 339
DJA_E1PTRADJCNT[15:0]
0x70013
Page 339
DJA_DS1PTRADJCNT[20:16]
340
Agere Systems Inc.
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