Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
14 Digital Jitter Attenuation Controller Registers (continued)
Table 488. DJA_E1PTRH—DJA_E1PTRL, E1 First-Order Loop Counter (R/W)
Address Bit
Name
Function
Reset
Default
0x70011 15:5
4:0
0x70012 15:0
RSVD
Reserved.
0x177000
DJA_E1PTRADJCNT[20:16] E1 First-Order Loop Count. Count value that
DJA_E1PTRADJCNT[15:0] determines the amount of time spent as a first-
order loop following a VT pointer adjustment in
E1 mode (see Table 635 on page 580).
Table 489. DJA_DS1PTRH—DJA_DS1PTRL, DS1 First-Order Loop Counter (R/W)
Address Bit
Name
Function
Reset
Default
0x70013 15:5
RSVD
Reserved.
0x11AB70
4:0 DJA_DS1PTRADJCNT[20:16] DS1 First-Order Loop Count. Count value that
0x70014 15:0 DJA_DS1PTRADJCNT[15:0] determines the amount of time spent as a first-
order loop following a VT pointer adjustment in
DS1 mode (see Table 635).
Table 490. DJA_DS1SELH—DJA_DS1SELL, DS1 E1 Mode Select (R/W)
Address
Bit
Name
Function
Reset
Default
0x70015 15:12
11:0
0x70016 15:0
RSVD
DJA_DS1SEL[28:17]
DJA_DS1SEL[16:1]
Reserved.
0xFFFFFFF
DS1 E1 Mode Select. Control signal that deter-
mines the operating mode of each jitter attenua-
tion block (1 = DS1, 0 = E1).
Table 491. DJA_CLK_CTL1—DJA_CLK_CTL4, Reference Clock Rate and Edge Transitions (R/W)
Address
Bit
Name
Function
Reset
Default
0x70017 15:14
13:12
RSVD
Reserved.
DJA_BLUECLKD1[1:0]
Reference Clock Rate. Control signal that indi-
cates that the input XCLK runs at 32 X (11) or
16 X (01) the line rate or exactly the line rate
(00).
111
0x70017 11:0
0x70018 15:0
DJA_TXEDGE[28:17]
DJA_TXEDGE[16:1]
Transmit Edge Select. Control signal that deter- 0xFFFFFFF
mines on which edge of the clock the output
DS1/E1 data transitions (1 = rising edge).
0x70019 15:12
11:0
0x7001A 15:0
RSVD
DJA_RXEDGE[28:17]
DJA_RXEDGE[16:1]
Reserved.
0xFFFFFFF
Receive Edge Select. Control signal that deter-
mines on which edge of the clock the input
DS1/E1 data is retimed (1 = rising edge).
Agere Systems Inc.
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ETC [ ETC ]
