Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
15.1 Test-Pattern Generation/Detection Register Descriptions
The following tables describe the functions of all bits in the microprocessor register map. For each address, the
register bits are indicated as either read/write (R/W) or read only (RO), and the value of the bits on reset is given.
Table 493. TPG_ID, Status Register (RO)
Address
Bit
Name
Function
Reset
Default
0x60000
15
TPG_READY
RSVD
This bit signifies that TPG reset/initialization is complete.
1
14:11
Reserved.
0x0
0x0
0x06
10:8 TPG_VERSION[2:0] These bits identify the version number of the TPG.
7:0 TPG_ID[7:0] TPG_ID returns a fixed value (0x06) when read.
Table 494. TPG_ISRC_OOFD, Delta Register (RO)
Address Bit
Name
Function
Reset
Default
0x60004 15:3
2
RSVD
Reserved.
0x0000
0
TPM_OOF2D
This bit is set when the TPM monitor E1 test signal out of
frame detector changes state (transitions).
1
0
RSVD
Reserved.
0
0
TPM_OOF0D
This bit is set when the TPM monitor DS1 test signal out of
frame detector changes state (transitions).
Table 495. TPG_ISRC_OOSD, Delta Register (RO)
Address Bit
Name
Function
Reset
Default
0x60005 15:6
5
RSVD
Reserved.
0x000
0
TPM_OOS5D
This bit is set when the TPM monitor DS3 test signal out-of-
sync detector changes state (transitions).
4
TPM_OOS4D
This bit is set when the TPM monitor DS3 test signal out-of-
sync detector changes state (transitions).
0
3
2
RSVD
Reserved.
0
0
TPM_OOS2D
This bit is set when the TPM monitor E1 test signal out of sync
detector changes state (transitions).
1
0
RSVD
Reserved.
0
0
TPM_OOS0D
This bit is set when the TPM monitor DS1 test signal out of
sync detector changes state (transitions).
Agere Systems Inc.
343
ETC [ ETC ]
