Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
13 Cross Connect (XC) Registers (continued)
13.2 Cross Connect Register Map
Table 479. Register Address Map
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Cross Connect Global—RO
XC_VERSION[2:0]
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x50000
Page 327
XC_ID_R
RSVD
XC_ID[7:0]
0x50001
—
0x5000D
Framer System Interface Control—R/W
0x5000E XC_CHI_MODE1_R
Page 327
0
XC_SYNC_FOR_DATA
XC_SI_CHI
0x5000F XC_CHI_MODE2_R
Page 327
XC_CHI_MODE7[1:0]
XC_CHI_MODE6[1:0]
XC_CHI_MODE5[1:0]
XC_CHI_MODE4[1:0]
XC_CHI_MODE3[1:0]
XC_CHI_MODE2[1:0]
XC_CHI_MODE1[1:0]
DS1/E1 Crosspoint Configuration—R/W
External I/O (LINETXDATA[1—29] and LINETXCLK[1—29] Pins) Data and Clock Output Selects
XC_PDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID
0x50010 XC_PIND_SRC[1—14]
XC_PDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID
—
0x5001D
Page 328
0x5001E
Page 328
XC_PIND_SRC15
RSVD
XC_PDATA29[7:0] Source_ID
0x5001F
DS1/E1 Crosspoint Configuration—R/W
Framer Receive Path Selects
XC_RP_RDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID
0x50020 XC_FRP_SRC[1—14]
—
0x5002D
Page 328
XC_RP_RDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID
XC_MDS1DATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID
XC_VDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID
0x5002E
0x5002F
RSVD
RSVD
DS1/E1 Crosspoint Configuration—R/W
M13 MUX Selects
0x50030 XC_M13_SRC[1—14]
—
0x5003D
Page 328
XC_MDS1DATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID
0x5003E
0x5003F
RSVD
RSVD
DS1/E1 Crosspoint Configuration—R/W
VT Mapper Selects
0x50040 XC_VT_SRC[1—14]
XC_VDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID
—
0x5004D
Page 329
0x5004E
0x5004F
RSVD
RSVD
Agere Systems Inc.
333
ETC [ ETC ]
