TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
13 Cross Connect (XC) Registers (continued)
Table 476. XC3_MDS3_SRC, XC3 DS3 Source Configuration (R/W)
Address Bit
Name
Function
Reset
Default
0x500D4 15:2
RSVD
Reserved.
0x0000
1:0 XC3_SOURCE_ID[1:0] DS3 Level Connections. This register defines the connec-
tivity at DS3 level among external I/O, M13, and SPE.
00 = M13 inputs/outputs DS3 through external pins.
01 = M13 and SPE pass data to each other.
10 = SPE inputs/outputs DS3 through external pins and M13
is used as a monitor for the transmit DS3.
11 = SPE inputs/outputs DS3 through external pins and M13
is used as a monitor for the receive DS3.
Table 477. XC_PINS_SRC[1—15], XC1 External I/O TXSYNC Source Configuration (R/W)
Address Bit
Name
Function
Reset
Default
0x500E0 15:8
—
0x500ED
XC_SYNC
[2, 4, . . . 28][7:0]
Source Identifier for External I/O Pin LINETXSYNC. (Even
channels.) In the LIU mode, these registers must be pro-
grammed the same as XC_PIND_SRC[1—15] (Table 463 on
page 328) registers; in the system interface mode (CHI, PSB,
and framer only), these registers will be programmed sepa-
rately to ensure the system data output properly.
0xFF
(invalid)
(SOURCE_ID)
0x500EE 15:8
RSVD
Reserved.
0x00
0xFF
0x500E0 7:0
—
0x500EE
XC_SYNC
[1, 3, . . . 29][7:0]
Source Identifier for External I/O Pin LINETXSYNC. (Odd
channels.)
(invalid)
Note: External I/O has 29 channels.
(SOURCE_ID)
Table 478. XC_ALCO_SRC[1—15], XC1 External I/O RXCLK Clock Out Source Configuration (R/W)
Address Bit
Name
Function
Reset
Default
0x500F0 15:8
—
0x500FD
XC_ALCO
[2, 4, . . . 28][7:0]
Source Identifier for External I/O Pin LINERXCLK when
Operating in Low Clock Output Mode. (Either DS1/E1 or
DS2.) For DS1/E1 channels, the programmed value of these
registers should be consistent with those of registers
XC_PIND_SRC[1—15] (Table 463 on page 328) to ensure
that clock and data for the same channel will always be routed
together; while for DS2 channels, the value of these registers
should match those of registers XC2_M23_SRC[1—7]
(Table 472 on page 330) (even channels).
0xFF
(invalid)
(SOURCE_ID)
0x500FE 15:8
RSVD
Reserved.
0x00
0xFF
0x500F0 7:0
—
0x500FE
XC_ALCO
[1, 3, . . . 29][7:0]
Source Identifier for External I/O Pin LINERXCLK when
Operating in Low Clock Output Mode. (Either DS1/E1 or
DS2.) For DS1/E1 channels, the programmed value of these
registers should be consistent with those of registers
XC_PIND_SRC[1—15] (Table 463 on page 328) to ensure
that clock and data for the same channel will always be routed
together; while for DS2 channels, the value of these registers
should match those of registers XC2_M23_SRC[1—7] (odd
channels).
(invalid)
(SOURCE_ID)
Note: External I/O has 29 channels.
332
Agere Systems Inc.
ETC [ ETC ]
