欢迎访问ic37.com |
会员登录 免费注册
发布采购

ILI9325 参数 Datasheet PDF下载

ILI9325图片预览
型号: ILI9325
PDF下载: 下载PDF文件 查看货源
内容描述: 的a-Si TFT LCD单芯片驱动器240RGBx320分辨率和26万色 [a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color]
分类和应用: 驱动器
文件页数/大小: 111 页 / 1190 K
品牌: ETC [ ETC ]
 浏览型号ILI9325的Datasheet PDF文件第25页浏览型号ILI9325的Datasheet PDF文件第26页浏览型号ILI9325的Datasheet PDF文件第27页浏览型号ILI9325的Datasheet PDF文件第28页浏览型号ILI9325的Datasheet PDF文件第30页浏览型号ILI9325的Datasheet PDF文件第31页浏览型号ILI9325的Datasheet PDF文件第32页浏览型号ILI9325的Datasheet PDF文件第33页  
a-Si TFT LCD Single Chip Driver  
240RGBx320 Resolution and 262K color  
ILI9325  
TRI  
0
DFM  
*
8-bit MPU System Interface Data Format  
system 8-bit interface (2 transfers/pixel) 65,536 colors  
1st Transfer  
2nd Transfer  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB  
10  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB  
10  
R5  
R4  
R3  
R2  
R1  
R0  
G5  
G4  
G3  
G2  
G1  
G0  
B5  
B4  
B3  
B2  
B1  
B0  
80-system 8-bit interface (3 transfers/pixel) 262,144 colors  
1st Transfer  
2nd Transfer  
3rd Transfer  
DB  
11  
DB  
10  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB  
10  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB  
10  
1
1
0
1
R5  
R4  
R3  
R2  
R1  
R0  
G5  
G4  
G3  
G2  
G1  
G0  
B5  
B4  
B3  
B2  
B1  
B0  
80-system 8-bit interface (3 transfers/pixel) 262,144 colors  
1st Transfer  
2nd Transfer  
3rd Transfer  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
R5  
R4  
R3  
R2  
R1  
R0  
G5  
G4  
G3  
G2  
G1  
G0  
B5  
B4  
B3  
B2  
B1  
B0  
Figure5 8-bit System Interface Data Format  
Data transfer synchronization in 8/9-bit bus interface mode  
ILI9325 supports a data transfer synchronization function to reset upper and lower counters which count the  
transfers numbers of upper and lower byte in 8/9-bit interface mode. If a mismatch arises in the numbers of  
transfers between the upper and lower byte counters due to noise and so on, the “00”h register is written 4  
times consecutively to reset the upper and lower counters so that data transfer will restart with a transfer of  
upper byte. This synchronization function can effectively prevent display error if the upper/lower counters are  
periodically reset.  
RS  
RD  
nWR  
Upper/  
Lower  
DB[17:9]  
“00”h  
“00”h  
“00”h  
“00”h  
Upper  
Lower  
8-/9-bit transfer  
synchronization  
Figure6 Data Transfer Synchronization in 8/9-bit System Interface  
7.3. Serial Peripheral Interface (SPI)  
The Serial Peripheral Interface (SPI) is selected by setting the IM[3:0] pins as “010x” level. The chip select pin  
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,  
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.  
Page 29 of 111  
Version: 0.35  
 复制成功!