Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
L3M
TXC-03452B
The Stuff/Sync Block and Build Blocks work together for mapping a DS3 signal into a TUG-3 or STS-1 SPE or
an E3 signal into a TUG-3. The mapped formats are shown in Figures 3 and 4. The stuffing algorithm for the
DS3 signal format uses one set of five control bits (C-bits) with one stuff opportunity bit (S-bit) for frequency
justification, per subframe (9 subframes). The E3 format uses five pairs of control bits (C1, C2 bits) to control
two stuff opportunity bits (S1 and S2) per subframe (one subframe per three rows for a total of three subframes
per frame). A read clock and timing indications are given by the Build Block for reading the transmit FIFO. A
FIFO overflow or underflow alarm indication is provided. Should an underflow/overflow condition occur, the
FIFO is immediately reset to the start-up preset value. The transmit FIFO also tracks the incoming line signal
that can have an average frequency error as high as +/- 20 ppm, and simultaneously accepts this signal with
up to 5 UI Peak-to-Peak jitter (where UI = 1/f).
The Build Block, with signals exchanged between itself and the Stuff/Sync Block, constructs one of two 87 col-
umn by 9 row formats: an ITU-TSS TUG-3 signal (Figure 3) or a SONET STS-1 (for STS-3) signal (Figure 4).
The L3M generates a stuff byte in column 0 when control bit NOPOH is set to 0, to fill out the 87 columns of the
SPE such that three L3M devices will provide inputs for a VC-4 of 261 columns, as shown in Figure 2. This col-
umn position is overwritten with the VC-4 POH when the device is mapped into the first TUG-3, while fixed stuff
is used for the second and third TUG-3s. A fixed pointer value of 6800H is used as the initial value when build-
ing a TUG-3 format. There are two levels of pointer movements in TUG-3 mapping. When the TUG-3 mode is
selected in drop timing mode, the transmit TUG-3 pointer value will change when there is a receive STM-1
AU-4 pointer increment or decrement. However, this feature may be disabled. Pointer movements on the
STM-1 bus, which are detected using the C1J1 and SPE bus signals, are compensated by creating a TUG-3
pointer movement in the opposite direction. An “O”-bit serial interface, or two bits in RAM, are used for map-
ping the two “O”-bits into the DS3 SONET format subframes. The “O”-bit interface consists of an output clock
(TOCHC) and an input data lead (TOCHD). The nine Path Overhead bytes are mapped individually into the
SONET format from either the POH interface (except the B3 byte), from microprocessor-written RAM positions,
or from internal logic (such as the path RDI state in bit 5 of G1). The POH interface consists of an output clock
(TPOHC), a framing pulse (TPOHF) and an input data lead (TPOHD). A control bit enables the POH interface
bytes to be written into RAM when transmitted. Enable bits are provided for controlling the FEBE and path RDI
states as a result of local alarms or remote status information received during ring operation. A B3 test mask or
fixed byte can also be transmitted. Control bits are provided for generating a TUG-3 path AIS, or an
unequipped status condition (payload and POH bytes are equal to zero). An alarm interface provides FEBE
and path RDI (FERF) input indications from a mate L3M device for ring operation. The alarm interface leads
consist of input data (TAIPD), framing pulse (TAIPF), and clock signal (TAIPC).
The Add Block uses an external byte rate clock signal (XCLKI), or the Add or Drop bus clock and the SPE and
C1J1 timing signals, for building and adding a TUG-3, STS-3/STS-1 SPE, or STS-1 SPE to the Add bus. The
Add Block supports the STM-1/STS-3 bus signaling rate of 19.44 MHz and the STS-1 signaling rate of 6.48
MHz. The external clock is enabled by placing a high on the external clock enable lead (XCLKE), and is
intended for STS-1 operation. The external clock generates the Add bus clock (ACLK), C1J1 indication
(AC1J1), and SPE indication (ASPE). The output data to the bus is 3-state, active true. A software control bit
enables the transport overhead A1, A2, C1, and H1/H2 bytes to be generated. The H1 and H2 bytes will carry
the value of 6000H and the C1 byte carries the value of 01H. An optional C1 signal (XC1 signal lead) can be
applied to the L3M device to align the start of the frame (A1, A2 bytes).
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TXC-03452B-MB
Ed. 6, April 2001
ETC [ ETC ]
