11.2.3
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
AECKSTP WDCKSTP PWCKSTP LDCKSTP
1
1
1
1
1
1
1
Initial value
Read/Write
1
—
—
—
—
R/W
R/W
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the PWM is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 1: PWM module standby mode control (PWCKSTP)
Bit 1 controls setting and clearing of module standby mode for the PWM.
PWCKSTP
Description
0
1
PWM is set to module standby mode
PWM module standby mode is cleared
(initial value)
328
ETC [ ETC ]
