Notes: 1. The setting should be made so that the error is not more than 1%.
2. The value set in BRR is given by the following equation:
OSC
N=
— 1
(64 × 22n × B)
where
B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
OSC: Value of øOSC (Hz)
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10-7.)
Table 10-7 Relation between n and Clock
SMR Setting
n
0
0
2
3
Clock
ø
øW/2*1/øW*2
CKS1
CKS0
0
0
1
1
0
1
0
1
ø/16
ø/64
Notes: 1. øW/2 clock is selected in active (medium- and high-speed) or sleep
(medium- and high-speed) mode.
2. øW clock is selected in subactive or subsleep mode. SCI3 can be used only
when the øW/2 is selected as the CPU clock in subactive or subsleep mode.
3. The error in table 10-6 is the value obtained from the following equation, rounded to two
decimal places.
B (rate obtained from n, N, OSC) — R (bit rate in left-hand column in table 10-6.)
Error (%) =
× 100
R (bit rate in left-hand column in table 10-6.)
Table 10-8 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10-8 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting
OSC (MHz)
Maximum Bit Rate (bit/s)
n
0
0
0
0
N
0
0
0
0
0.0384*
600
2
31250
38400
62500
2.4576
4
Note:
*
When SMR is set up to CKS1 = “0”, CKS0 = “1”.
284
ETC [ ETC ]
