8. Bit rate register (BRR)
Bit
7
BRR7
1
6
BRR6
1
5
BRR5
1
4
BRR4
1
3
BRR3
1
2
BRR2
1
1
BRR1
1
0
BRR0
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
Table 10-6 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
Table 10-6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
OSC
32.8 kHz
38.4 kHz
2 MHz
2.4576 MHz
4 MHz
n
Bit Rate
(bit/s)
Error
(%)
Error
(%)
Error
(%)
Error
(%)
Error
(%)
n
N
n
N
n
N
n
2
3
3
0
3
3
2
2
0
0
0
—
0
N
21
3
N
110
Cannot be used,
as error exceeds
3%
—
0
—
3
—
0
—
2
—
12
—
–0.83 —
—
—
150
0.16
0
0
2
25
—
0.16
—
200
0
2
0
0
155 0.16
124
103 0.16
2
—
250
—
0
—
1
—
0
0
0
153 –0.26 0
249
12
0
300
0
1
0
1
0
7
3
1
—
0
0
0
0
0
0
0
0
—
0
2
0.16
600
0
0
0
0
51
25
12
—
—
—
—
—
0.16
0.16
0.16
—
0
103 0.16
1200
2400
4800
9600
19200
31250
38400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
51
25
12
—
—
1
0.16
0.16
0.16
—
0
0
—
—
—
—
—
0
—
—
—
0
—
—
—
0
—
—
—
—
283
ETC [ ETC ]
