3. Event counter L (ECL)
ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The
event clock from the external asynchronous event AEVL pin is used as the input clock source.
ECL can be cleared to H'00 by software, and is also initialized to H'00 upon reset.
Bit
7
6
5
4
3
ECL3
0
2
ECL2
0
1
ECL1
0
0
ECL0
0
ECL7
ECL6
ECL5
ECL4
0
0
0
Initial Value
Read/Write
0
R
R
R
R
R
R
R
R
4. Clock stop register 2 (CKSTPR2)
Bit
7
6
—
1
5
—
1
4
—
1
3
2
1
0
—
AECKSTP WDCKSTP PWCKSTP LDCKSTP
1
1
1
1
Initial value
Read/Write
1
—
—
—
—
R/W
R/W
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the asynchronous event counter is described here. For details of
the other bits, see the sections on the relevant modules.
Bit 3: Asynchronous event counter module standby mode control (AECKSTP)
Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter.
AECKSTP
Description
0
1
Asynchronous event counter is set to module standby mode
Asynchronous event counter module standby mode is cleared
(initial value)
246
ETC [ ETC ]
