4. Register configuration
Table 9-20 shows the register configuration of the asynchronous event counter.
Table 9-20 Asynchronous Event Counter Registers
Name
Abbrev.
ECCSR
ECH
R/W
R/W
R
Initial Value
H'00
Address
H'FF95
H'FF96
H'FF97
H'FFFB
Event counter control/status register
Event counter H
H'00
Event counter L
ECL
R
H'00
Clock stop register 2
CKSTP2
R/W
H'FF
9.7.2
Register Descriptions
1. Event counter control/status register (ECCSR)
Bit
7
OVH
0
6
OVL
0
5
4
3
CUEH
0
2
CUEL
0
1
0
—
CH2
CRCH
0
CRCL
0
0
0
Initial Value
Read/Write
*
*
R/(W)
R/(W)
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
242
ETC [ ETC ]
