Bit 1: Counter reset control H (CRCH)
Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to
this bit, the counter reset is cleared and the ECH count-up function is enabled.
Bit 1
CRCH
Description
0
1
ECH is reset
(initial value)
ECH reset is cleared and count-up function is enabled
Bit 0: Counter reset control L (CRCL)
Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to
this bit, the counter reset is cleared and the ECL count-up function is enabled.
Bit 0
CRCL
Description
0
1
ECL is reset
(initial value)
ECL reset is cleared and count-up function is enabled
2. Event counter H (ECH)
Bit
7
6
5
4
3
ECH3
0
2
ECH2
0
1
ECH1
0
0
ECH0
0
ECH7
ECH6
ECH5
ECH4
0
0
0
Initial Value
Read/Write
0
R
R
R
R
R
R
R
R
ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL.
Either the external asynchronous event AEVH pin or the overflow signal from lower 8-bit counter
ECL can be selected as the input clock source by bit CH2. ECH can be cleared to H'00 by
software, and is also initialized to H'00 upon reset.
245
ETC [ ETC ]
