9.3.4
Timer C Operation States
Table 9-7 summarizes the timer C operation states.
Table 9-7 Timer C Operation States
Sub-
Sub-
Module
Operation Mode
Reset
Active
Sleep
Watch
active
sleep
Standby Standby
TCC
Interval
Reset
Functions Functions Halted
Functions/ Functions/ Halted
Halted* Halted*
Halted
Auto reload Reset
Reset
Functions Functions Halted
Functions/ Functions/ Halted
Halted* Halted*
Halted
TMC
Functions Retained Retained Functions Retained Retained Retained
Note:
*
When øw/4 is selected as the TCC internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/ø (s). When the counter is operated in subactive mode or subsleep mode, either
select øw/4 as the internal clock or select an external clock. The counter will not
operate on any other internal clock. If øw/4 is selected as the internal clock for the
counter when øw/8 has been selected as subclock øSUB, the lower 2 bits of the counter
operate on the same cycle, and the operation of the least significant bit is unrelated to
the operation of the counter.
196
ETC [ ETC ]
