Bits 6 and 5: Counter up/down control (TMC6, TMC5)
Selects whether TCC up/down control is performed by hardware using UD pin input, or whether
TCC functions as an up-counter or a down-counter.
Bit 6
Bit 5
TMC6
TMC5
Description
0
0
1
0
1
*
TCC is an up-counter
TCC is a down-counter
(initial value)
Hardware control by UD pin input
UD pin input high: Down-counter
UD pin input low: Up-counter
*: Don't care
Bits 4 and 3: Reserved bits
Bits 4 and 3 are reserved; they are always read as 1 and cannot be modified.
Bits 2 to 0: Clock select (TMC2 to TMC0)
Bits 2 to 0 select the clock input to TCC. For external event counting, either the rising or falling
edge can be selected.
Bit 2
Bit 1
Bit 0
TMC2
TMC1
TMC0
Description
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Internal clock: ø/8192
Internal clock: ø/2048
Internal clock: ø/512
Internal clock: ø/64
(initial value)
0
0
0
1
Internal clock: ø/16
1
Internal clock: ø/4
1
Internal clock: øW/4
1
External event (TMIC): rising or falling edge*
Note:
*
The edge of the external event signal is selected by bit IEG1 in the IRQ edge select
register (IEGR). See 1. IRQ edge select register (IEGR) in 3.3.2 for details. IRQ2 must
be set to 1 in port mode register 1 (PMR1) before setting 111 in bits TMC2 to TMC0.
192
ETC [ ETC ]
