APEX 20K Programmable Logic Device Family Data Sheet
Table 33. APEX 20KE Device DC Operating Conditions
Notes (6), (7)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
High-level LVTTL, CMOS, or 3.3-V
PCI input voltage
1.7, 0.5 × VCCIO
(8)
4.1
V
VIL
Low-level LVTTL, CMOS, or 3.3-V
PCI input voltage
–0.5
0.8, 0.3 × VCCIO
(8)
V
V
V
V
V
V
V
V
V
V
VOH
3.3-V high-level LVTTL output
voltage
IOH = –12 mA DC,
2.4
V
CCIO = 3.00 V (9)
3.3-V high-level LVCMOS output IOH = –0.1 mA DC,
VCCIO – 0.2
0.9 × VCCIO
2.1
voltage
V
CCIO = 3.00 V (9)
3.3-V high-level PCI output voltage
IOH = –0.5 mA DC,
VCCIO = 3.00 to 3.60 V (9)
IOH = –0.1 mA DC,
2.5-V high-level output voltage
V
CCIO = 2.30 V (9)
IOH = –1 mA DC,
CCIO = 2.30 V (9)
IOH = –2 mA DC,
CCIO = 2.30 V (9)
2.0
V
1.7
V
VOL
3.3-V low-level LVTTL output
voltage
IOL = 12 mA DC,
0.4
0.2
VCCIO = 3.00 V (10)
3.3-V low-level LVCMOS output
voltage
I
OL = 0.1 mA DC,
CCIO = 3.00 V (10)
V
3.3-V low-level PCI output voltage IOL = 1.5 mA DC,
0.1 × VCCIO
V
CCIO = 3.00 to 3.60 V
(10)
2.5-V low-level output voltage
I
OL = 0.1 mA DC,
VCCIO = 2.30 V (10)
OL = 1 mA DC,
CCIO = 2.30 V (10)
IOL = 2 mA DC,
CCIO = 2.30 V (10)
VI = 4.1 to –0.5 V (11)
Tri-stated I/O pin leakage current VO = 4.1 to –0.5 V (11)
0.2
0.4
0.7
V
V
V
I
V
V
II
Input pin leakage current
–10
–10
10
10
µA
µA
IOZ
ICC0
VCC supply current (standby)
(All ESBs in power-down mode)
VI = ground, no load, no
toggling inputs, -1 speed
grade
10
5
mA
VI = ground, no load, no
toggling inputs,
mA
-2, -3 speed grades
RCONF
Value of I/O pin pull-up resistor
before and during configuration
VCCIO = 3.0 V (12)
VCCIO = 2.375 V (12)
VCCIO = 1.71 V (12)
20
30
60
50
80
k¾
k¾
k¾
150
Altera Corporation
67
ETC [ ETC ]
