APEX 20K Programmable Logic Device Family Data Sheet
Single-Port Mode
The APEX 20K ESB also supports a single-port mode, which is used when
simultaneous reads and writes are not required. See Figure 22.
Figure 22. ESB in Single-Port Mode
Note (1)
Dedicated Inputs &
Global Signals
Dedicated Clocks
RAM/ROM
2 or 4
(2)
4
128 × 16
256 × 8
512 × 4
1,024 × 2
2,048 × 1
data[ ]
Data In
D
Q
to MegaLAB,
FastTrack &
Local
ENA
Data Out
D
Q
Interconnect
ENA
address[ ]
Address
D
Q
ENA
wren
outclken
Write Enable
inclken
inclock
D
Q
Write
Pulse
Generator
ENA
outclock
Notes:
(1) All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or the chip-wide reset.
(2) APEX 20KE devices have four dedicated clocks.
Content-Addressable Memory
In APEX 20KE devices, the ESB can implement CAM. CAM can be
thought of as the inverse of RAM. When read, RAM outputs the data for
a given address. Conversely, CAM outputs an address for a given data
word. For example, if the data FA12is stored in address 14, the CAM
outputs 14when FA12is driven into it.
CAM is used for high-speed search operations. When searching for data
within a RAM block, the search is performed serially. Thus, finding a
particular data word can take many cycles. CAM searches all addresses in
parallel and outputs the address storing a particular word. When a match
is found, a match flag is set high. Figure 23 shows the CAM block
diagram.
34
Altera Corporation
ETC [ ETC ]
