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EP20K200RC208-1 参数 Datasheet PDF下载

EP20K200RC208-1图片预览
型号: EP20K200RC208-1
PDF下载: 下载PDF文件 查看货源
内容描述: 现场可编程门阵列(FPGA)的\n [Field Programmable Gate Array (FPGA) ]
分类和应用: 现场可编程门阵列
文件页数/大小: 114 页 / 1501 K
品牌: ETC [ ETC ]
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APEX 20K Programmable Logic Device Family Data Sheet  
Figure 18. Deep Memory Block Implemented with Multiple ESBs  
Address Decoder  
ESB  
ESB  
ESB  
to System Logic  
The ESB implements two forms of dual-port memory: read/ write clock  
mode and input/ output clock mode. The ESB can also be used for  
bidirectional, dual-port memory applications in which two ports read or  
write simultaneously. To implement this type of dual-port memory, two  
or four ESBs are used to support two simultaneous reads or writes. This  
functionality is shown in Figure 19.  
Figure 19. APEX 20K ESB Implementing Dual-Port RAM  
Port A  
address_a[]  
data_a[]  
Port B  
address_b[]  
data_b[]  
we_a  
we_b  
clkena_a  
clkena_b  
Clock A  
Clock B  
Altera Corporation  
31  
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