Si3035
Control Registers
Any register not listed here is reserved and should not be written.
Table 20. Register Summary
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DL
Bit 0
SB
1
2
3
4
5
6
7
8
Control 1
SR
Control 2
AL
HBE
RXE
Control 3
Control 4
DAA Control 1
DAA Control 2
PLL1 Divide N1
OPOL
PDL
ONHM
PDN
RDT
OHE
OH
CPE
ATM1
ARM1
ATM0
ARM0
N1[7:0]
PLL1 Multiply
M1
M1[7:0]
9
PLL2 Div./Mult.
N2/M2
N2[3:0]
M2[3:0]
10
11
12
13
PLL Control
CGM
Chip Revision
Line Side Status
REVA[3:0]
LCS[3:0]
CLE
FDT
Transmit and
Receive Gain
CBID
REVB[3:0]
ARX
ATX
DCE
ARX0
0
14
15
Daisy-Chain
Control
NSLV2
TXM
NSLV1
ATX2
NSLV0
ATX1
SSEL1
SSEL0
RXM
1
FSD
ARX2
0
RPOL
ARX1
0
TX/RX Gain
Control
ATX0
IIRE
16
17
IIR Filter Control
Calibration
0
0
0
0
MCAL
CALD
34
Rev. 1.2
ETC [ ETC ]
