RTL8100C & RTL8100CL
Datasheet
Bit
R/W
Symbol
Description
3
R
SPEED_10
Speed. Set when current media is 10Mbps. Reset, when current media
is 100Mbps.
2
1
0
R
R
R
LINKB
TXPF
RXPF
Inverse of Link status.
0: Link OK
1: Link Fail.
Transmit Pause Flag.
Set when the RTL8100C(L) sends a pause packet. Reset when the
RTL8100C(L) sends a timer done packet.
Receive Pause Flag.
Set when the RTL8100C(L) is in backoff state because a pause packet
was received.
Reset when the pause state is cleared.
5.21. CONFIG 3: Configuration Register3
(Offset 0059h, R/W)
Table 21. CONFIG 3: Configuration Register3
Bit
R/W
Symbol
Description
7
R
GNTSel
Grant Select.
Sets the Frame’s asserted time after the Grant signal has been
asserted. Frame and Grant are PCI signals.
1: Delay one clock from GNT assertion
0: No delay
6
R/W
PARM_En
Parameter Enable (Used in 100Mbps mode only).
0: The 9346CR register EEM1:0 = [1:1] will enable the
PHY1_PARM, PHY2_PARM, and TW_PARM registers to be written
via software.
1: Allows parameters to be auto-loaded from the 93C46, and disables
writing to PHY1_PARM, PHY2_PARM and TW_PARM registers
via software. PHY1_PARM and PHY2_PARM can be auto-loaded
from the EEPROM in this mode. The parameter auto-load process is
executed each time the Link is OK in 100Mbps mode.
Single-Chip Fast Ethernet Controller
25
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
