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RTL8100CL 参数 Datasheet PDF下载

RTL8100CL图片预览
型号: RTL8100CL
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理单芯片快速以太网控制器 [SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT]
分类和应用: 外围集成电路控制器LTE局域网以太网以太网:16GBASE-T
文件页数/大小: 73 页 / 652 K
品牌: ETC [ ETC ]
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RTL8100C & RTL8100CL  
Datasheet  
5.17. 9346CR: 93C46 Command Register  
(Offset 0050h, R/W)  
This register is used for issuing commands to the RTL8100C(L). These commands are issued by setting the  
corresponding bits for the function. A warm software reset along with individual reset and enable/disable for  
transmitter and receiver are also provided.  
Table 17. 9346CR: 93C46 Command Register  
Bit  
R/W  
Symbol  
Description  
7-6  
R/W  
EEM1-0  
Operating Mode: These 2 bits set the RTL8100C(L) operating mode.  
EEM1 EEM0 Operating Mode  
0
0
Normal: RTL8100C(L) network/host  
communication mode.  
0
1
Auto-load: Entering this mode will force the  
RTL8100C(L) to load the contents of the  
93C46 as if an RSTB signal had been asserted.  
This auto-load operation will take about 2ms.  
After it is completed, the RTL8100C(L) goes  
back to normal mode automatically  
(EEM1 = 0 EEM0 = 0) and all other  
registers are reset to default values.  
1
1
0
1
93C46 Programming: In this mode, both  
network and host bus master operations are  
disabled. The 93C46 can be directly accessed  
via bit3-0 which now reflects the states of  
EECS, EESK, EEDI, & EEDO pins  
respectively.  
Config Register Write Enable: Before writing  
to CONFIG0, 1, 3, 4 registers, and bit 13, 12,  
and 8 of BMCR (offset 62h-63h), the  
RTL8100C(L) must be placed in this mode.  
This will protect the RTL8100C(L)’s  
configuration from accidental change.  
4-5  
3
2
1
0
-
-
Reserved.  
R/W  
R/W  
R/W  
R
EECS  
EESK  
EEDI  
EEDO  
These bits reflect the state of EECS, EESK, EEDI, and EEDO pins in  
auto-load or 93C46 programming mode.  
Single-Chip Fast Ethernet Controller  
22  
Track ID: JATR-1076-21 Rev. 1.06