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RTL8100CL 参数 Datasheet PDF下载

RTL8100CL图片预览
型号: RTL8100CL
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理单芯片快速以太网控制器 [SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT]
分类和应用: 外围集成电路控制器LTE局域网以太网以太网:16GBASE-T
文件页数/大小: 73 页 / 652 K
品牌: ETC [ ETC ]
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RTL8100C & RTL8100CL  
Datasheet  
5.18. CONFIG 0: Configuration Register 0  
(Offset 0051h, R/W)  
Table 18. CONFIG 0: Configuration Register 0  
Bit  
R/W  
Symbol  
Description  
7
R
SCR  
Scrambler Mode.  
Always 0.  
6
R
R
R
-
PCS  
T10  
PCS Mode.  
Always 0.  
5
10Mbps Mode.  
Always 0.  
10Mbps Medium Type.  
Always (PL1, PL0) = (1, 0).  
Reserved.  
4-3  
2-0  
PL1, PL0  
-
5.19. CONFIG 1: Configuration Register 1  
(Offset 0052h, R/W)  
Table 19. CONFIG 1: Configuration Register 1  
Bit  
R/W  
Symbol  
Description  
7-6  
R/W  
LEDS1-0  
Refer to section 5.5 LED Interface, page 8, for a detailed LED pin description. The  
initial value of these bits comes from the 93C46.  
5
R/W  
DVRLOAD  
Driver Load.  
Software may use this bit to make sure that the driver has been loaded.  
1: Driver loaded  
0: Driver not loaded  
When the command register bits IOEN, MEMEN, and BMEN of the PCI  
configuration space are written, the RTL8100C(L) will clear this bit  
automatically.  
4
R/W  
LWACT  
LWAKE active mode: The LWACT bit and LWPTN bit in CONFIG4 register  
are used to program the LWAKE pin’s output signal. Depending on the  
combination of these two bits, there may be 4 choices of LWAKE signal, i.e.,  
active high, active low, positive (high) pulse, and negative (low) pulse. The  
output pulse width is about 150ms.  
The default value of each of these two bits is 0, i.e., the default output signal of  
the LWAKE pin is an active high signal.  
LWAKE Output  
LWPTN  
LWACT  
0
1
Active high*  
Active low  
0
1
Positive pulse  
Negative pulse  
* Default value.  
3
2
R
R
MEMMAP  
IOMAP  
Memory Mapping.  
Operational registers are mapped into PCI memory space.  
I/O Mapping.  
Operational registers are mapped into PCI I/O space.  
Single-Chip Fast Ethernet Controller  
23  
Track ID: JATR-1076-21 Rev. 1.06