RTL8100C & RTL8100CL
Datasheet
5.22. CONFIG 4: Configuration Register4
(Offset 005Ah, R/W)
Table 22. CONFIG 4: Configuration Register4
Bit
R/W
Symbol
Description
7
R/W
RxFIFOAutoClr
Receive FIFO buffer Auto Clear.
When set to 1, the RTL8100C(L) will clear the Rx FIFO buffer
automatically.
6
5
R/W
R/W
AnaOff
Analog Power Off.
This bit cannot be auto-loaded from EEPROM (93C46).
1: Turns off the analog power of the RTL8100C(L) internally
0: Normal working state. This is also the power-on default value
Long Wake-up Frame.
LongWF
The initial value comes from EEPROM auto load.
0: The RTL8100C(L) supports up to 8 wake-up frames, each with
masked bytes selected from offset 12 to 75
1: The RTL8100C(L) supports up to 5 wake-up frames, each with a
16-bit CRC algorithm for MS Wakeup Frame support. The low byte
of the 16-bit CRC should be placed in the corresponding CRC
register, and the high byte of the 16-bit CRC should be placed in the
corresponding LSB CRC register.
Wake-up frames 0 and 1 are the same as above, except that the
masked bytes start from offset 0 to 63. Wake-up frames 2 and 3 are
merged into one long wake-up frame with masked bytes selected from
offset 0 to 127. Wake-up frames 4, 5, 6, and 7 are merged into another
2 long wake-up frames. Refer to 6.5 PCI Power Management
Functions, page 45, for a detailed description.
LWAKE vs. PMEB.
4
R/W
LWPME
1: LWAKE can only be asserted when PMEB is asserted and
ISOLATEB is low
0: LWAKE and PMEB are asserted at the same time
Reserved.
LWAKE Pattern.
3
2
-
-
R/W
LWPTN
See the LWACT bit in Table 19. CONFIG 1: Configuration Register
1, page 23.
1
0
-
-
Reserved.
Pre-Boot Wakeup.
R/W
PBWakeup
The initial value comes from EEPROM auto load.
1: Pre-Boot Wakeup disabled (suitable for CardBus and MiniPCI
applications)
0: Pre-Boot Wakeup enabled
Single-Chip Fast Ethernet Controller
27
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
