4.2 NCO-Related Registers
4.2.1 Register 12
7
6
5
4
3
2
1
0
SYNCOK FIFO_ALARM
MASK_SYNC MASK_FIFO
SYNCOK
ERF_STORE NCO_EVENT MASK_ERF
_STORE
_STORE
OK
_ALARM
SYNCOK
State of SYNCOK Pin
R/W 7
This value reflects the actual state of the SYNCOK pin.
This signal is slow enough to be sampled by the external
microcontroller. When this bit is 1, sync is achieved.
When this bit is 0, sync is not achieved. The reset value
is 0.
SYNCOK_STORE
R 6
This read-only bit is set to 1 if a faulty SYNCOK condition
is detected since the last read. If this bit is 0, it indicates
that the sync lock status continues to be positive. The
reset value is 0.
FIFO_ALARM_STORE
R 5
This read-only bit is set to 1 if a FIFO alarm condition is
detected since the last read. If this bit is 0, no FIFO alarm
condition was detected. The reset value is 0.
ERF_STORE Error Flag Store
R 4
This read-only bit is set to 1 if an error flag is inserted
since the last read. If this bit is 0, no error flag was
inserted. The reset value is 0.
NCO_EVENT
R/W 3
If this bit is 1, the NCO measurement is complete or the
AUTO ACQUISITION has terminated. The reset value is 0.
MASK_ERF Error Flag Mask
If this bit is 1, an error flag insertion in the MPEG
R/W 2
transport packet does not generate an interrupt. If this bit
is 0, an error flag insertion does generate an interrupt.
The reset value is 0.
4-10
Register Descriptions
ETC [ ETC ]
