MAP_OFF
AMPL
QAM Mapping Off
R/W 2
When this bit is 1, the L64777 stops QAM mapping.
When this bit is 0, the L64777 uses DVB-compliant
mapping. The reset value is 0.
PLL Oscillator Amplitude
R/W 1
This controls the amplitude of the on-chip PLL oscillator.
When this bit is 0, the L64777 is in low-power mode with
higher jitter. When this bit is 1, the L64777 is in
high-power mode with lower jitter. For normal operation,
set this bit to 0.
RES
Reserved
0
This bit is reserved.
4.1.8 Registers 7 and 8
15 14
RES
0
ICNT_O
RES
Reserved
15
This bit is reserved.
ICNT_O
Initial OCLK Value
R/W [14:0]
This is a 15-bit initial value for the OCLK PLL feedback
division. The reset value for bit 3 is 1; for all other bits it
is 0.
4.1.9 Registers 9 and 10
15 14
RES
0
ICNT_I
RES
Reserved
15
This bit is reserved.
ICNT_I
Initial ICLK Value
R/W [14:0]
This is a 15-bit initial value for the ICLK PLL reference
division. The reset value for bit 1 is 1; for all other bits it
is 0.
4-8
Register Descriptions
ETC [ ETC ]
